Leakage current reduction in electrical isolation gate structures

Patent metadata

Field	Value
Publication number	US-11469226-B2
Application number	US-202016913770-A
Country	US
Kind code	B2
Filing date	Jun 26, 2020
Priority date	Oct 10, 2018
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

In an embodiment, an integrated circuit includes transistors in different active regions, electrically isolated using single diffusion break isolation. The single diffusion break isolation includes a first dummy transistor that has a different threshold voltage than the transistors in either active region for which the single diffusion break is creating isolation. The first dummy transistor may have lower leakage current than transistors in either active region, creating effective isolation between the active regions and consuming relatively small amounts of power due to the lower leakage currents.

First claim

What is claimed is:

1. An integrated circuit comprising:
a first active region within a first diffusion region of a first conductivity type, wherein the first active region includes a plurality of first transistors having a first threshold voltage, wherein a first transistor of the plurality of first transistors has a first gate formed from a first plurality of layers of materials, and wherein the first threshold voltage is dependent on the materials in the first plurality of layers of materials and the order of the first plurality of layers;
a second active region within the first diffusion region, wherein the second active region includes a plurality of second transistors having a second threshold voltage different than the first threshold voltage, wherein a second transistor of the plurality of second transistors has a second gate formed from a second plurality of layers of materials, wherein the second threshold voltage is dependent on the materials in the second plurality of layers of materials and the order of the second plurality of layers; and
a single diffusion break isolation between the first active region and the second active region, wherein the single diffusion break isolation includes a single transistor having a third threshold voltage greater than the first threshold voltage and the second threshold voltage, wherein the single transistor has a single gate formed from a third plurality of layers of materials, wherein the third threshold voltage is dependent on the third plurality of layers of materials and the order of the third plurality of layers, wherein there is at least one difference between the first plurality of layers of materials and the second plurality of layers of materials, wherein there is at least one difference between the first plurality of layers of materials and the third plurality of layers of materials, and wherein there is at least one difference between the third plurality of layers of materials and the second plurality of layers of materials.

2. The integrated circuit as recited in claim 1 wherein a leakage current in the single transistor is less than a leakage current in the first transistor, and wherein the leakage current in the single transistor is less than a leakage current in the second transistor.

3. The integrated circuit as recited in claim 1 wherein the single gate is coupled to a fixed voltage input during operation that ensures that the single transistor is off during operation.

4. The integrated circuit as recited in claim 3 further comprising:
a third active region within a second diffusion region, wherein the second diffusion region has a second conductivity type different from the first conductivity type, wherein the third active region includes a plurality of third transistors having a fourth threshold voltage, wherein a third transistor of the plurality of third transistors has a third gate formed from a fourth plurality of layers of materials, and wherein the fourth threshold voltage is dependent on the materials in the fourth plurality of layers of materials and the order of the fourth plurality of layers;
a fourth active region within the second diffusion region, wherein the fourth active region includes a plurality of fourth transistors having a fifth threshold voltage different than the fourth threshold voltage, wherein a fourth transistor of the plurality of fourth transistors has a fourth gate formed from a fifth plurality of layers of materials, wherein the fifth threshold voltage is dependent on the materials in the fifth plurality of layers of materials and the order of the fifth plurality of layers; and
a second single diffusion break isolation between the third active region and the fourth active region within the second diffusion region, wherein the second single diffusion break isolation includes a second single transistor having a second single gate formed from a sixth plurality of layers of materials and aligned to the single gate of the single transistor, wherein the second single transistor has a sixth threshold voltage greater than the fourth threshold voltage and the fifth threshold voltage, wherein the sixth threshold voltage is dependent on the materials in the sixth plurality of layers of materials and the order of the sixth plurality of layers, and wherein there is at least one difference between the fourth plurality of layers of materials and the fifth plurality of layers of materials, wherein there is at least one difference between the fourth plurality of layers of materials and the sixth plurality of layers of materials, and wherein there is at least one difference between the fifth plurality of layers of materials and the sixth plurality of layers of materials.

5. The integrated circuit as recited in claim 4 wherein the second single gate is coupled to a second fixed voltage input during operation that ensures that the second single transistor is off during operation, wherein the second fixed voltage input is different than the fixed voltage input.

6. The integrated circuit as recited in claim 1 wherein the plurality of first transistors, the plurality of second transistors, and the single transistor are fin field effect transistors (FinFETs).

7. An integrated circuit comprising:
a first diffusion region of a first conductivity type, wherein the first diffusion region comprises:
a plurality of first transistors having a first threshold voltage, wherein a first plurality of layers of materials forming gates of the plurality of first transistors are a factor in the first threshold voltage;
a plurality of second transistors having a second threshold voltage different than the first threshold voltage, wherein a second plurality of layers of materials forming gates of the plurality of second transistors are a factor in the second threshold voltage; and
a single diffusion break isolation between the first plurality of transistors and the second plurality of transistors, wherein the single diffusion break isolation includes a single transistor having a single gate, wherein the single transistor has a third threshold voltage that is greater than the first threshold voltage and the second threshold voltage, and wherein a third plurality of layers of materials forming the single gate are a factor in the third threshold voltage, and wherein there is at least one difference between the third plurality of layers of materials and the first plurality of layers of materials, and wherein there is at least one difference between the third plurality of layers of materials and the second plurality of layers of materials.

8. The integrated circuit as recited in claim 7 wherein there is at least one difference between the first plurality of layers of materials and the second plurality of layers of materials.

9. The integrated circuit as recited in claim 7 wherein the difference is at least one of an order of the third plurality of layers of materials and a type of material in a given layer of the third plurality of layers of materials.

10. The integrated circuit are cited in claim 7 wherein the first plurality of layers of materials are a dominant factor in the first threshold voltage.

11. The integrated circuit as recited in claim 7 wherein the first plurality of layers of materials are a primary factor in the first threshold voltage.

12. The integrated circuit as recited in claim 7 further comprising:
a second diffusion region of a second conductivity type different than the first conductivity type, wherein the second diffusion region comprises:
a plurality of third transistors having a fourth threshold voltage, wherein a fourth plurality of layers of materials forming gates of the plurality of third tran

Assignees

• Apple Inc

Inventors

• Alptekin Emre
• Hoffmann Thomas

Classifications

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• H01L27/0886

  Electricity · mapped topic

• H01L27/0883 Primary

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic

• H10D89/10

  Integrated device layouts · CPC title