Three-dimensional (3D) integrated circuit device having a backside power delivery network

Patent metadata

Field	Value
Publication number	US-11444068-B2
Application number	US-202016928939-A
Country	US
Kind code	B2
Filing date	Jul 14, 2020
Priority date	Jul 14, 2020
Publication date	Sep 13, 2022
Grant date	Sep 13, 2022

Abstract

An integrated circuit (IC) package is described. The IC package includes a power delivery network. The IC package also includes a first die having a first surface and a second surface, opposite the first surface. The second surface is on a first surface of the power delivery network. The IC package further includes a second die having a first surface on the first surface of the first die. The IC package also includes package bumps on a second surface of the power delivery network, opposite the first surface of the power delivery network. The package bumps are coupled to contact pads of the power delivery network.

First claim

What is claimed is:

1. An integrated circuit (IC) package, comprising:
a power delivery network comprising a bonding material layer as a first outer surface layer of the power delivery network, the power delivery network further comprising a second outer surface layer that is opposite the bonding material layer, the bonding material layer partially surrounding interconnects that are exposed to an active layer of a first die;
the first die having a first outer surface layer and the active layer as a second outer surface layer, opposite the first outer surface layer, the active layer directly on the bonding material layer and the interconnects of the power delivery network;
a second die having a first outer surface layer directly on the first outer surface layer of the first die; and
package bumps on the second outer surface layer of the power delivery network and coupled to contact pads of the power delivery network.

2. The IC package of claim 1 ,
in which the first die comprises:
first active devices;
a first back-end-of-line (BEOL) metallization structure coupled to the first active devices; and
first contact pads in the first outer surface layer of the first die and coupled to the first BEOL metallization structure; and

in which the second die comprises:
second active devices;
a second BEOL metallization structure coupled to the second active devices; and
second contact pads in the first outer surface layer of the second die and coupled to the second BEOL metallization structure, in which the second contact pads of the second die are directly on the first contact pads of the first die.

3. The IC package of claim 1 , in which the power delivery network comprises:
an oxide layer as the second outer surface layer of the power delivery network, wherein the contact pads of the power delivery network are placed within the oxide layer.

4. The IC package of claim 1 , in which the first outer surface layer of the first die is directly bonded to the first outer surface layer of the second die.

5. The IC package of claim 1 , in which the first die comprises a logic die and the second die comprises a memory die.

6. The IC package of claim 1 , in which a first layer of the power delivery network comprises an oxide material.

7. The IC package of claim 1 , in which the package bumps comprise package solder balls coupled to the contact pads of the power delivery network.

8. An integrated circuit (IC) package, comprising:
a power delivery network; comprising a bonding material layer as a first outer surface layer of the power delivery network, the power delivery network further comprising a second outer surface layer that is opposite the bonding material layer, the bonding material layer partially surrounding interconnects that are exposed to an active layer of a first die;
the first die having a first outer surface layer and the active layer as a second outer surface layer, opposite the first outer surface layer, the active layer directly on the bonding material layer and the interconnects of the power delivery network;
means for storing data having a first outer surface layer directly on the first outer surface layer of the first die; and
package bumps on the second outer surface layer of the power delivery network and coupled to contact pads of the power delivery network.

9. The IC package of claim 8 , in which a first layer of the power delivery network comprises an oxide material.

10. The IC package of claim 8 , in which the package bumps comprise package solder balls coupled to the contact pads of the power delivery network.

Assignees

• Qualcomm Inc

Inventors

• Song Stanley Seungchul
• Kim Jonghae
• Chidambaram Periannan
• Kamal Pratyush

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/01

  Manufacture or treatment · CPC title

• H10W72/0198

  batch processes · CPC title