Three-dimensional (3D) integrated circuit device having a backside power delivery network
US-11444068-B2 · Sep 13, 2022 · US
This page is not indexed by search engines while we improve data quality.
Kamal Pratyush patents
Kamal Pratyush is listed as an inventor on 27 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Kamal Pratyush |
| Total patents | 27 |
| First publication | Jan 15, 2015 |
| Latest publication | Sep 13, 2022 |
Notable patents
Publications ranked by popularity score, then publication date.
Three-dimensional (3d) integrated circuit device having a backside power delivery network
US-2022020735-A1 · Jan 20, 2022 · US
Power distribution networks for a three-dimensional (3d) integrated circuit (ic) (3dic)
US-2019027435-A1 · Jan 24, 2019 · US
Power distribution networks for a three-dimensional (3D) integrated circuit (IC) (3DIC)
US-10121743-B2 · Nov 6, 2018 · US
Power distribution networks for a three-dimensional (3d) integrated circuit (ic) (3dic)
US-2018286800-A1 · Oct 4, 2018 · US
Silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) standard library cell circuits having a gate back-bias rail(s), and related systems and methods
US-10062680-B2 · Aug 28, 2018 · US
Connection propagation for inter-logical block connections in integrated circuits
US-9929733-B1 · Mar 27, 2018 · US
Power gate placement techniques in three-dimensional (3D) integrated circuits (ICs) (3DICs)
US-9754923-B1 · Sep 5, 2017 · US
Three dimensional logic circuit
US-9537471-B2 · Jan 3, 2017 · US
Clock tree synthesis for low cost pre-bond testing of 3D integrated circuits
US-9508615-B2 · Nov 29, 2016 · US
Recent patents
Latest publications not already listed above.
Clock tree synthesis for low cost pre-bond testing of 3d integrated circuits
US-2016233134-A1 · Aug 11, 2016 · US
Three dimensional logic circuit
US-2016233853-A1 · Aug 11, 2016 · US
High quality physical design for monolithic three-dimensional integrated circuits (3d ic) using two-dimensional integrated circuit (2d ic) design tools
US-2016042110-A1 · Feb 11, 2016 · US
Monolithic three dimensional (3D) integrated circuit (IC) (3DIC) cross-tier clock skew management systems, methods and related components
US-9213358-B2 · Dec 15, 2015 · US
PLACEMENT OF MONOLITHIC INTER-TIER VIAS (MIVs) WITHIN MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) USING CLUSTERING TO INCREASE USABLE WHITESPAC
US-2015333005-A1 · Nov 19, 2015 · US
Silicon-on-insulator (soi) complementary metal oxide semiconductor (cmos) standard library cell circuits having a gate back-bias rail(s), and related systems and methods
US-2015325563-A1 · Nov 12, 2015 · US
Monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) with vertical memory components, related systems and methods
US-9147438-B2 · Sep 29, 2015 · US
Placement of monolithic inter-tier vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace
US-9123721-B2 · Sep 1, 2015 · US
Length-of-diffusion protected circuit and method of design
US-9093995-B2 · Jul 28, 2015 · US
Decoupling capacitor for integrated circuit
US-9053960-B2 · Jun 9, 2015 · US
PLACEMENT OF MONOLITHIC INTER-TIER VIAS (MIVs) WITHIN MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) USING CLUSTERING TO INCREASE USABLE WHITESPACE
US-2015145143-A1 · May 28, 2015 · US
Monolithic three dimensional (3d) integrated circuit (ic) (3dic) cross-tier clock skew management systems, methods and related components
US-2015121327-A1 · Apr 30, 2015 · US
MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) WITH VERTICAL MEMORY COMPONENTS, RELATED SYSTEMS AND METHODS
US-2015109843-A1 · Apr 23, 2015 · US
METHODS OF DESIGNING THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) AND RELATED SYSTEMS AND COMPONENTS
US-2015112646-A1 · Apr 23, 2015 · US
Monolithic three dimensional (3D) flip-flops with minimal clock skew and related systems and methods
US-9013235-B2 · Apr 21, 2015 · US
Monolithic three dimensional (3d) flip-flops with minimal clock skew and related systems and methods
US-2015022250-A1 · Jan 22, 2015 · US
Monolithic three dimensional (3d) random access memory (ram) array architecture with bitcell and logic partitioning
US-2015019802-A1 · Jan 15, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Qualcomm Inc | 27 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D88/00 | 17 |
| H10W90/00 | 11 |
| H01L27/0688 | 9 |
| H01L23/5226 | 8 |
| H10W72/01 | 7 |