Embedded packages, methods of fabricating the same, electronic systems including the same, and memory cards including the same

Patent metadata

Field	Value
Publication number	US-2016118337-A1
Application number	US-201514717624-A
Country	US
Kind code	A1
Filing date	May 20, 2015
Priority date	Oct 23, 2014
Publication date	Apr 28, 2016
Grant date	—

Abstract

An embedded package includes a chip having a top surface on which a connection member is disposed, a first insulation layer surrounding a portion of the chip, a second insulation layer disposed on the first insulation layer to cover the chip, circuit patterns disposed on a bottom surface of the first insulation layer, a third insulation layer disposed on the bottom surface of the first insulation layer to cover the circuit patterns, an external connection terminal penetrating the third insulation layer to contact any one of the circuit patterns, a metal layer disposed on a top surface of the second insulation layer, a first via penetrating the first insulation layer to electrically couple the connection member to any one of the circuit patterns, and a second via penetrating the first and second insulation layers to electrically couple the metal layer to any one of the circuit patterns.

First claim

What is claimed is:

1 . An embedded package comprising:
a chip having a top surface on which a connection member is disposed; a first insulation layer surrounding a portion of the chip; a second insulation layer disposed on the first insulation layer so that a bottom surface of the second insulation layer contacts a top surface of the first insulation layer and the second insulation layer covers the chip; a plurality of circuit patterns disposed on a bottom surface of the first insulation layer; a third insulation layer disposed on the bottom surface of the first insulation layer to cover the plurality of circuit patterns; an external connection terminal penetrating the third insulation layer to contact any one of the plurality of circuit patterns; a metal layer disposed on a top surface of the second insulation layer; a first via penetrating the first insulation layer to electrically couple the connection member to any one of the circuit patterns; and a second via penetrating the first and second insulation layers to electrically couple the metal layer to any one of the circuit patterns.

2 . The embedded package of claim 1 , wherein the chip is disposed to face down so that the top surface of the chip is configured to face downwardly in the first and second insulation layers.

3 . The embedded package of claim 1 , wherein the first insulation layer surrounds the top surface and sidewalls of the chip.

4 . The embedded package of claim 3 , wherein the second insulation layer covers a bottom surface of the chip.

5 . The embedded package of claim 4 , wherein the bottom surface of the chip is substantially coplanar with the top surface of the first insulation layer.

6 . The embedded package of claim 1 , wherein the first, second and third insulation layers include a same material.

7 . The embedded package of claim 6 , wherein the first, second and third insulation layers include a resin-coated-copper (RCC) layer.

8 . The embedded package of claim 7 , wherein the plurality of circuit patterns, the metal layer, the first via and the second via are formed by an electroplating process performed using a copper layer of the RCC layer as a seed layer.

9 . The embedded package of claim 1 , wherein the second via is disposed to be spaced apart from the chip.

10 . An embedded package comprising:
a chip having a top surface on which connection members are disposed; a first insulation layer surrounding a portion of the chip; a second insulation layer disposed on the first insulation layer so that a bottom surface of the second insulation layer contacts a top surface of the first insulation layer and the second insulation layer covers the chip; a plurality of circuit patterns disposed on a bottom surface of the first insulation layer; a third insulation layer disposed on the bottom surface of the first insulation layer to cover the plurality of circuit patterns; an external connection terminal penetrating the third insulation layer to contact any one of the plurality of circuit patterns; a metal layer disposed on a top surface of the second insulation layer; first vias penetrating the first insulation layer to electrically couple the connection members to the circuit patterns; and second vias penetrating the first and second insulation layers to electrically couple the metal layer to the circuit patterns, wherein distances between the second vias and the chip are different.

11 . The embedded package of claim 10 , wherein the chip is disposed to face down so that the top surface of the chip is configured to face downwardly in the first and second insulation layers.

12 . The embedded package of claim 10 , wherein the first insulation layer surrounds the top surface and sidewalls of the chip.

13 . The embedded package of claim 12 , wherein the second insulation layer covers a bottom surface of the chip.

14 . The embedded package of claim 13 , wherein the bottom surface of the chip is substantially coplanar with the top surface of the first insulation layer.

15 . The embedded package of claim 10 , wherein the first, second and third insulation layers include a same material.

16 . The embedded package of claim 15 , wherein the first, second and third insulation layers include a resin-coated-copper (RCC) layer.

17 . The embedded package of claim 16 , wherein the plurality of circuit patterns, the metal layer, the first vias and the second vias are formed by an electroplating process performed using a copper layer of the RCC layer as a seed layer.

18 . The embedded package of claim 10 , wherein the second vias includes:
outer vias arrayed on an outer closed loop line which is adjacent to sidewalls of the first and second insulation layers; inner vias arrayed on an inner closed loop line surrounded by the outer closed loop line and spaced apart from the chip; and middle vias arrayed on a middle closed loop line between the outer closed loop line and the inner closed loop line, wherein the outer vias and the middle vias are arrayed in a zigzag fashion along edges of the first and second insulation layers, and wherein the inner vias and the middle vias are arrayed in a zigzag fashion along the edges of the first and second insulation layers.

19 . An embedded package comprising:
a first chip having a top surface on which first connection members are disposed; a second chip having a top surface on which second connection members are disposed and having a bottom surface to which a bottom surface of the first chip is attached; a first insulation layer surrounding a portion of the first chip; a second insulation layer surrounding a portion of the second chip; a third insulation layer disposed between the first and second insulation layers; a plurality of first circuit patterns disposed on a bottom surface of the first insulation layer; a plurality of second circuit patterns disposed on a top surface of the second insulation layer; a fourth insulation layer disposed on the bottom surface of the first insulation layer to cover the plurality of first circuit patterns; an external connection terminal penetrating the fourth insulation layer to contact any one of the plurality of first circuit patterns; a fifth insulation layer disposed on the top surface of the second insulation to cover the plurality of second circuit patterns; a metal layer disposed on a top surface of the fifth insulation layer; lower vias penetrating the first insulation layer to electrically couple the first connection members to the first circuit patterns; upper vias penetrating the second insulation layer to electrically couple the second connection members to the second circuit patterns; first through electrodes and second through electrodes penetrating the first, second and third insulation layers to electrically couple the first circuit patterns to the second circuit patterns; and connection vias penetrating the fifth insulation layer to electrically couple the metal layer to the second circuit patterns.

20 . The embedded package of claim 19 ,
wherein the first chip is disposed to face down so that the top surface of the first chip faces downwardly in the first insulation layer; and wherein the second chip is disposed to face up so that the top surface of the second chip faces upwardly in the second insulation layer.

Assignees

• Sk Hynix Inc

Inventors

• Yoon Sang Hoon
• Moon Ki Il
• Kim Myoung Seob
• Song Yun Mi

Classifications

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/9413

  on encapsulations · CPC title