Package structure and method for forming the same

Patent metadata

Field	Value
Publication number	US-9859229-B2
Application number	US-201615227060-A
Country	US
Kind code	B2
Filing date	Aug 3, 2016
Priority date	Apr 28, 2016
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

Package structures and methods for forming the same are provided. The package structure includes an integrated circuit die and a first shielding feature over a base layer. The package structure also includes a package layer encapsulating the integrated circuit die and the first shielding feature. The package structure further includes a second shielding feature extending from the side surface of the base layer towards the first shielding feature to electrically connect to the first shielding feature. The side surface of the second shielding feature faces away from the side surface of the base layer and is substantially coplanar with the side surface of the package layer.

First claim

What is claimed is:

1. A package structure, comprising:
an integrated circuit die and a first shielding feature over a front surface of a base layer;
a package layer encapsulating the integrated circuit die and the first shielding feature; and
a second shielding feature extending from a back surface of the base layer along a side surface of the base layer towards the first shielding feature to electrically connect to the first shielding feature, wherein the second shielding feature has a corner surrounded by the first shielding feature.

2. The package structure as claimed in claim 1 , wherein the second shielding feature is in direct contact with the corner of the first shielding feature in the package layer.

3. The package structure as claimed in claim 1 , wherein the second shielding feature partially laterally overlaps the first shielding feature and the integrated circuit die.

4. The package structure as claimed in claim 1 , further comprising a redistribution structure over the first shielding feature, wherein the second shielding feature has a side surface opposite to the side surface of the base layer, and the side surface of the second shielding feature is substantially coplanar with a side surface of the redistribution structure and a side surface of the package layer.

5. The package structure as claimed in claim 1 , further comprising a redistribution structure over the first shielding feature and the package layer, wherein a distance between the second shielding feature and the redistribution structure is less than a thickness of the package layer.

6. The package structure as claimed in claim 1 , further comprising a redistribution structure between the first shielding feature and the base layer, wherein the second shielding feature has a side surface opposite to the side surface of the base layer, and the side surface of the second shielding feature is non-coplanar with a side surface of the redistribution structure.

7. The package structure as claimed in claim 1 , further comprising one or more conductive features encapsulated by the package layer and between the first shielding feature and the integrated circuit die.

8. The package structure as claimed in claim 1 , further comprising a second integrated circuit die stacked over the integrated circuit die and the package layer, wherein the second shielding feature further extends to surround the second integrated circuit die.

9. A package structure, comprising:
an integrated circuit die encapsulated by a package layer;
a first shielding feature penetrating through the package layer;
a second shielding feature covering the integrated circuit die and the package layer, wherein the second shielding feature extends towards the first shielding feature to electrically connect to the first shielding feature, and the second shielding feature has a corner surrounded by the first shielding feature; and
a redistribution structure electrically connected to the first shielding feature, wherein a portion of the first shielding feature is sandwiched between the redistribution structure and the second shielding feature such that the second shielding feature is separated from the redistribution structure.

10. The package structure as claimed in claim 9 , wherein a portion of the package layer is sandwiched between the redistribution structure and the second shielding feature such that the second shielding feature is further separated from the redistribution structure.

11. The package structure as claimed in claim 9 , wherein the portion of the first shielding feature sandwiched between the redistribution structure and the second shielding feature is thinner than the package layer.

12. The package structure as claimed in claim 9 , further comprising:
a conductive feature encapsulated by the package layer and between the first shielding feature and the integrated circuit die; and
a connecting feature between the conductive feature and the first shielding feature, wherein the first shielding feature is electrically connected to the conductive feature through the connecting feature.

13. The package structure as claimed in claim 9 , further comprising conductive features encapsulated by the package layer and between the first shielding feature and the integrated circuit die, wherein the first shielding feature laterally overlaps more than one of the conductive features.

14. A method for forming a package structure, comprising:
forming a first shielding feature over a front surface of a base layer;
disposing an integrated circuit die over the front surface of the base layer;
forming a package layer over the front surface of the base layer to encapsulate the first shielding feature and the integrated circuit die;
forming an opening penetrating through the base layer and extending into the package layer so that a bottom surface of the opening is within the package layer; and
forming a second shielding feature covering the integrated circuit die and the package layer, wherein the second shielding feature extends from a back surface of the base layer into the opening to electrically connect to the first shielding feature in the package layer.

15. The method for forming a package structure as claimed in claim 14 , further comprising forming a redistribution structure over the base layer before the formation of the first shielding feature, wherein the opening further penetrates through the redistribution structure.

16. The method for forming a package structure as claimed in claim 14 , further comprising forming one or more conductive features over the base layer during the formation of the first shielding feature, wherein the one or more conductive features are encapsulated by the package layer.

17. The method for forming a package structure as claimed in claim 14 , further comprising stacking a second integrated circuit die before the formation of the opening, wherein the second integrated circuit die and the integrated circuit die are on two opposite sides of the base layer, and the second integrated circuit die is surrounded by the second shielding feature.

18. The method for forming a package structure as claimed in claim 14 , wherein the first shielding feature and the package layer are partially removed during the formation of the opening such that the opening extends into the first shielding feature and the package layer.

19. The method for forming a package structure as claimed in claim 14 , further comprising dicing the second shielding feature along the opening.

20. The method for forming a package structure as claimed in claim 16 , further comprising dicing the first shielding feature during the formation of the opening, wherein the one or more conductive features between the first shielding feature and the integrated circuit die are not cut during the formation of the opening.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Yu-Peng
• Weng Sheng-Feng
• Chiu Sheng-Hsiang
• Chen Meng-Tse
• Lin Chih-Wei
• Lin Wei-Hung
• Cheng Ming-Da
• Hsieh Ching-Hua
• Liu Chung-Shi

Classifications

• H05K9/0073

  Shielding materials (H05K9/0003 takes precedence) · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title