Multi channel semiconductor device having multi dies and operation method thereof

Patent metadata

Field	Value
Publication number	US-11443794-B2
Application number	US-201916289747-A
Country	US
Kind code	B2
Filing date	Mar 1, 2019
Priority date	Jul 9, 2014
Publication date	Sep 13, 2022
Grant date	Sep 13, 2022

Abstract

An operation method of a semiconductor device is disclosed. The semiconductor device includes separate first and second dies in a package and receives first types of signals through first and second respective channels independent of each other and corresponding to the first and second respective dies. The method includes a step in which when information for controlling internal operations of the first and second dies is first applied to the first die through a first pad, the first die performs the internal operation and also transmits the information to the second die through an internal interface connecting the first die and the second die, and a step in which when the information is transmitted to the second die, the second die performs the internal operation.

First claim

What is claimed is:

1. An operation method of a semiconductor device that includes a first die and a second die in a package and receives a first control signal for controlling the first die and the second die, the method comprising:
a first step in which when the first control signal is received by the first die through a first pad, the first die generates first control information based on the received first control signal and transmits the first control information to the second die through an internal interface connecting the first die and the second die; and
a second step in which when the first control information is transmitted to the second die, the second die performs an internal operation,
wherein the first control signal is one of a reset signal for resetting operations of the first die and the second die and a ZQ signal for ZQ calibration operations of the first die and the second die.

2. The operation method of the semiconductor device of claim 1 , wherein the first die and the second die are each packaged directly on a same, single package substrate.

3. The operation method of the semiconductor device of claim 1 ,
wherein the first die and the second die are independently packaged on different package substrates.

4. The operation method of the semiconductor device of claim 1 , wherein the internal interface is one of a wired interface and a wireless interface for information interfacing between the first die and the second die.

5. The operation method of the semiconductor device of claim 4 , wherein the internal interface is a wired interface that includes at least one of an interposer, a wire bonding and a printed circuit board.

6. The operation method of the semiconductor device of claim 4 , wherein the internal interface is a wireless interface that performs an optical communication.

7. The operation method of the semiconductor device of claim 1 ,
wherein the first die and the second die have the same storage capacity and physical size as each other.

8. The operation method of the semiconductor device of claim 1 , wherein the first die and second die form a DDR DRAM performing the same data access operation as a 2 channel single die.

9. The operation method of claim 1 , wherein each of the first die and the second die is a memory die.

10. A semiconductor device comprising:
a package substrate;
a first die and a second die disposed on the package substrate respectively, the first die having a first channel and a first pad configured to receive a first control signal for controlling the first die, and the second die having a second channel and a second pad configured to receive the first control signal for controlling the second die, the first control signal being received either by the first die or by the second die, wherein the first die is configured to: when the first control signal is received by the first die, generate a first control information based on the received first control signal, and the second die is configured to: when the first control signal is received by the second die, generate the first control information based on the received first control signal; and
a first internal interface connecting the first and second dies, wherein the first die is further configured to: when the first control information is generated by the first die, transmit the first control information to the second die through the first internal interface for controlling the second die, and the second die is further configured to: when the first control information is generated by the second die, transmit the first control information to the first die through the first internal interface for controlling the first die,
wherein the first and second dies are the same in storage capacity and physical size, and are disposed horizontally adjacent to each other on the package substrate.

11. The semiconductor device of claim 10 , wherein each of the first and second dies further includes a control logic, and the control logic is configured to generate the first control information upon receiving the first control signal.

12. The semiconductor device of claim 11 , wherein the first control signal is a ZQ signal.

13. The semiconductor device of claim 12 , wherein:
the first control information controls on-resistance values and on-termination values of an output driver; and
each control logic of the first and second dies is further configured to generate an internal control signal upon receiving the ZQ signal for controlling on-resistance values and on-termination values of an output driver of the first and second dies receiving the ZQ signal.

14. The semiconductor device of claim 10 , wherein the first internal interface includes a wireless transmission channel for transmitting signals between the first and second dies.

15. The semiconductor device of claim 10 , wherein the package substrate is a first package substrate, the first die is part of a first package on a second package substrate, and the second die is part of a second package on a third package substrate, such that the first and second dies and respective second and third package substrates mounted on the first package substrate form a package including first and second packages mounted on the first package substrate.

16. A semiconductor device comprising:
a package substrate;
a first die disposed on the package substrate;
a second die;
the first die having a first channel and a first pad configured to receive a ZQ control signal for controlling the first die, and
the second die having a second channel and a second pad configured to receive the ZQ control signal for controlling the second die,
the ZQ control signal being received either by the first die or by the second die,
wherein, the first die is configured to, when the ZQ control signal is received by the first die, generate a second signal based on the received the ZQ control signal by the first die; and
a first internal interface connecting the first and second dies, wherein, the first die is further configured to, when the second signal is generated by the first die, transmit the second signal to the second die through the first internal interface for controlling the second die,
wherein the first and second dies are the same in storage capacity and physical size.

17. The semiconductor device of claim 16 , wherein:
the second die is configured to, when the ZQ control signal is received by the second die, generate the second signal based on the ZQ control signal received by the second die; and
the second die is further configured to, when the second signal is generated by the second die, transmit the second signal to the first die through the first internal interface for controlling the first die.

18. The semiconductor device of claim 17 , wherein each of the first and second dies further includes a control logic, and the control logic is configured to generate the second signal upon receiving the ZQ control signal.

19. The semiconductor device of claim 18 , wherein:
the second signal controls on-resistance values and on-termination values of an output driver.

20. The semiconductor device of claim 16 , further comprising:
a third die disposed on the package substrate; and
a fourth die;
wherein the third and fourth dies are the same in storage capacity and physical size.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Eom Yoon-Joo
• Park Joon-Young
• Bae Yongcheol
• Lee Won Young
• Jang Seongjin
• Choi Junghwan
• Choi Joosun

Classifications

• G11C11/4096 Primary

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C2207/105

  Aspects related to pads, pins or terminals · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title