Semiconductor device having interconnection in package and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10734059-B2
Application number	US-201916674554-A
Country	US
Kind code	B2
Filing date	Nov 5, 2019
Priority date	Jul 9, 2014
Publication date	Aug 4, 2020
Grant date	Aug 4, 2020

Abstract

A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.

First claim

What is claimed is:

1. A dynamic random access memory (DRAM) package for communicating with an external device through two independent channels, the DRAM package comprising:
a package substrate;
a first DRAM die configured to be connected to a first independent channel;
a second DRAM die, identical to the first DRAM die in physical size and storage capacity, configured to be connected to a second independent channel; and
an interconnection circuit configured to electrically connect the first and second DRAM dies for transmitting and receiving signals between the first and second DRAM dies,
wherein the first and the second DRAM dies are disposed on horizontally separate areas of the package substrate and do not vertically overlap each other, and the first and the second DRAM die are packaged together in a package,
wherein the first DRAM die includes a first swapping circuit configured to exchange input signals received from the first independent channel in response to a first swapping signal,
wherein the input signals received from the first independent channel are address signals, and
wherein the package is configured such that an impedance calibration signal is sent to the second DRAM die through the interconnection circuit when the impedance calibration signal is generated in the first DRAM die.

2. The DRAM package of claim 1 , wherein the address signals include an address 0 signal, an address 1 signal, an address 2 signal, an address 3 signal, an address 4 signal, and an address 5 signal, and the first swapping circuit is further configured to swap the address 5 signal of the address signals for the address 0 signal of the address signals in response to the first swapping signal.

3. The DRAM package of claim 2 , wherein the first swapping circuit is further configured to swap the address 4 signal of the address signals for the address 1 signal of the address signals in response to the first swapping signal.

4. The DRAM package of claim 3 , wherein the first swapping circuit is configured to swap all of the address 5 through address 0 signals of the address signals in response to the first swapping signal.

5. The DRAM package of claim 4 , wherein the interconnection circuit includes a wire bonding.

6. The DRAM package of claim 1 , wherein the package is configured such that the second DRAM die includes a second swapping circuit configured to exchange input signals received from the second independent channel in response to a second swapping signal.

7. The DRAM package of claim 6 , wherein the package is further configured such that the first swapping signal is enabled when the second swapping signal is disabled, and the first swapping signal is disabled when the second swapping signal is enabled.

8. The DRAM package of claim 1 , wherein the DRAM package further includes a first pad set configured to be connected to the first independent channel and a second pad set configured to be connected to the second independent channel, and
wherein the first pad set and the second pad set are located at a first edge and a second edge of the package substrate respectively in which the first edge and the second edge are opposite edges of the package substrate.

9. The DRAM package of claim 8 , wherein the first DRAM die and the second DRAM die include a third pad set and a fourth pad set respectively, and
wherein each pad of the third pad set is connected to a corresponding pad of the first pad set of the package substrate and each pad of the fourth pad set is connected to a corresponding pad of the second pad set of the package substrate.

10. The DRAM package of claim 9 , wherein the first DRAM die and the second DRAM die further include a fifth pad set and a sixth pad set respectively, and
wherein each pad of the fifth pad set is connected to a corresponding pad of the sixth pad set by the interconnection circuit.

11. The DRAM package of claim 10 , wherein the first DRAM die is disposed in a position for the third pad set of the first DRAM die to be adjacent to the first edge of the package, and
wherein the second DRAM die is disposed in a position for the fourth pad set of the second DRAM die to be adjacent to the second edge of the package substrate.

12. The DRAM package of claim 11 , wherein the first DRAM die and the second DRAM die disposed on the package substrate are identical in configuration, and
wherein the second DRAM die is rotated by one hundred eighty degrees relative to the first DRAM die.

13. A dynamic random access memory (DRAM) package for communicating with an external device through two independent channels, the DRAM package comprising:
a package substrate;
a first DRAM die configured to be connected to a first independent channel;
a second DRAM die, identical to the first DRAM die in physical size and storage capacity, configured to be connected to a second independent channel; and
an interconnection circuit configured to electrically connect the first and second DRAM dies for transmitting and receiving signals between the first and second DRAM dies,
wherein the first and the second DRAM dies are packaged together in a package,
wherein the first DRAM die includes a first swapping circuit configured to exchange input signals received from the first independent channel in response to a first swapping signal,
wherein the input signals received from the first independent channel are address signals, and
wherein the package is configured such that an impedance calibration signal is sent to the second DRAM die through the interconnection circuit when the impedance calibration signal is generated in the first DRAM die.

14. The DRAM package of claim 13 , wherein the address signals include an address 0 signal, an address 1 signal, an address 2 signal, an address 3 signal, an address 4 signal, and an address 5 signal, and the first swapping circuit is further configured to swap the address 5 signal of the address signals for the address 0 signal of the address signals in response to the first swapping signal.

15. The DRAM package of claim 14 , wherein the first swapping circuit is further configured to swap the address 4 signal of the address signals for the address 1 signal of the address signals in response to the first swapping signal.

16. The DRAM package of claim 15 , wherein the first swapping circuit is configured to swap all of the address 5 through address 0 signals of the address signals in response to the first swapping signal.

17. The DRAM package of claim 13 , wherein the package is configured such that the second DRAM die includes a second swapping circuit configured to exchange input signals received from the second independent channel in response to a second swapping signal.

18. The DRAM package of claim 17 , wherein the package is further configured such that the first swapping signal is enabled when the second swapping signal is disabled, and the first swapping signal is disabled when the second swapping signal is enabled.

19. A dynamic random access memory (DRAM) package for communicating with an external device through two independent channels, the DRAM package comprising:
a package substrate;
a first DRAM die configured to be connected to a first independent channel;
a second DRAM die, identical to the first DRAM die in physical size and storage capacity, configured to be connected to a second independent channel; and
an interconnection circuit configured to electrically connect the first and second DRAM dies for transmitting and receiving

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jaehyung
• Kim Jungsik
• Lee Youngdae
• Kim Duyeul
• Yim Sungmin
• Park Kwangil
• Park Chulsung

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• G11C29/022 Primary

  in I/O circuitry · CPC title

• H10B80/00 Primary

  Assemblies of multiple devices comprising at least one memory device covered by this subclass · CPC title

• G11C7/109

  Control signal input circuits · CPC title