Semiconductor device having interconnection in package and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10971208-B2
Application number	US-202016734821-A
Country	US
Kind code	B2
Filing date	Jan 6, 2020
Priority date	Jul 9, 2014
Publication date	Apr 6, 2021
Grant date	Apr 6, 2021

Abstract

A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.

First claim

What is claimed is:

1. A dynamic random access memory (DRAM) package for communicating with an external device through a first channel and a second channel, the DRAM package comprising:
a package substrate;
a first pad part including first through sixth channel address pads of the first channel respectively receiving first through sixth address signals of the first channel, the first pad part being disposed at a first edge of the package substrate;
a second pad part including first through sixth channel address pads of the second channel respectively receiving first through sixth address signals of the second channel, the second pad part being disposed at a second edge of the package substrate, the second edge being opposite to the first edge;
a first DRAM die disposed on the package substrate, the first DRAM die including first through sixth die address pads of the first channel respectively connected to the first through sixth channel address pads of the first channel;
a second DRAM die identical to the first DRAM die in physical size and storage capacity and rotated by one hundred eighty degrees relative to the first DRAM die, the second DRAM die including first through sixth die address pads of the second channel respectively connected to the sixth through first channel address pads of the second channel; and
an interconnection circuit configured to electrically connect the first and second DRAM dies, the interconnection circuit including at least one wire bonding through which an impedance calibration signal is transmitted from the first DRAM die to the second DRAM die,
wherein the first through sixth channel address pads of the first channel and the first through sixth channel address pads of the second channel are substantially line-symmetrical with respect to a center line of the DRAM package, the center line of the DRAM package is between the first edge and the second edge,
wherein the first and second DRAM dies are packaged together in the DRAM package,
wherein the second DRAM die further includes a swapping circuit configured to receive the first through sixth address signals of the second channel through the sixth through first die address pads of the second channel and the first through sixth channel address pads of the second channel, and exchange the first through sixth address signals of the second channel in response to a swapping signal, and
wherein the impedance calibration signal is generated by the first DRAM die and is based on information received from the first pad part.

2. The DRAM package of claim 1 , wherein the swapping circuit is further configured to swap the sixth address signal of the second channel for the first address signal of the second address channel in response to the swapping signal.

3. The DRAM package of claim 2 , wherein the swapping circuit is further configured to swap the fifth address signal of the second channel for the second address signal of the second channel in response to the swapping signal.

4. The DRAM package of claim 3 , wherein the swapping circuit is further configured to swap all of the sixth through first address signals of the second channel in response to the swapping signal.

5. The DRAM package of claim 1 , wherein the first DRAM die further includes a first swapping circuit configured to receive the first through sixth address signals of the first channel through the first through sixth die address pads of the first channel and the first through sixth channel address pads of the first channel, and exchange the first through sixth address signals of the first channel in response to a first swapping signal, and
wherein the swapping circuit is a second swapping circuit and the swapping signal is a second swapping signal.

6. The DRAM package of claim 5 , configured such that the first swapping signal is enabled when the second swapping signal is disabled, and the first swapping signal is disabled when the second swapping signal is enabled.

7. A dynamic random access memory (DRAM) package for communicating with an external device through a first channel and a second channel, the DRAM package comprising:
a package substrate;
a first pad part including first through eighth channel DQ pads of the first channel respectively receiving first through eighth DQ signals of the first channel, the first pad part being disposed at a first edge of the package substrate;
a second pad part including first through eighth channel DQ pads of the second channel respectively receiving first through eighth DQ signals of the second channel, the second pad part being disposed at a second edge of the package substrate, the second edge being opposite to the first edge;
a first DRAM die disposed on the package substrate, the first DRAM die including first through eighth die DQ pads of the first channel respectively connected to the first through eighth channel DQ pads of the first channel;
a second DRAM die identical to the first DRAM die in physical size and storage capacity and rotated by one hundred eighty degrees relative to the first DRAM die, the second DRAM die including first through eighth die DQ pads of the second channel respectively connected to the eighth through first channel DQ pads of the second channel; and
an interconnection circuit configured to electrically connect the first and second DRAM dies, the interconnection circuit including at least one wire bonding through which an impedance calibration signal is transmitted from the first DRAM die to the second DRAM die,
wherein an order of the first through eighth die DQ pads of the first channel is equal to an order of the first through eighth channel DQ pads of the first channel with respect to a third edge of the package substrate in a plan view,
wherein an order of the first through eighth die DQ pads of the second channel is different from an order of the first through eighth channel DQ pads of the second channel with respect to the third edge of the package substrate in a plan view,
wherein the first and second DRAM dies are packaged together in the DRAM package, and
wherein the impedance calibration signal is generated by the first DRAM die and is based on information received from the first pad part.

8. The DRAM package of claim 7 , wherein the first DRAM die and the second DRAM die further include a third pad part and a fourth pad part respectively, and
wherein each pad of the third pad part is connected to a corresponding pad of the fourth pad part by the interconnection circuit.

9. The DRAM package of claim 8 , wherein the first DRAM die is disposed in a direction for the first through eighth die DQ pads of the first channel to be adjacent to the first edge of the DRAM package and the second DRAM die is disposed in a direction for the first through eighth die DQ pads of the second channel to be adjacent to the second edge of the DRAM package.

10. The DRAM package of claim 7 , wherein the first pad part further includes first through sixth channel address pads of the first channel respectively receiving first through sixth address signals of the first channel,
wherein the second pad part further includes first through sixth channel address pads of the second channel respectively receiving first through sixth address signals of the second channel,
wherein the first DRAM die further includes first through sixth die address pads of the first channel respectively connected to the first through sixth channel address pads of the first channel, and
wherein the second DRAM die further includes first through sixth die address pads of the second channel respectively connected to the sixth through first channel address pads of the second channel.

11. The DRAM package of claim

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jaehyung
• Kim Jungsik
• Lee Youngdae
• Kim Duyeul
• Yim Sungmin
• Park Kwangil
• Park Chulsung

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• G11C29/022 Primary

  in I/O circuitry · CPC title

• G11C11/408

  Address circuits · CPC title

• G11C7/1075

  for multiport memories each having random access ports and serial ports, e.g. video RAM · CPC title