Field effect transistor with elevated active regions and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9859422-B2
Application number	US-201514723868-A
Country	US
Kind code	B2
Filing date	May 28, 2015
Priority date	May 28, 2015
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A field effect transistor having a higher breakdown voltage can be provided by forming a contiguous dielectric material layer over gate stacks, forming via cavities laterally spaced from the gate stacks, selectively depositing a single crystalline semiconductor material, and converting upper portions of the deposited single crystalline semiconductor material into elevated source/drain regions. Lower portions of the selectively deposited single crystalline semiconductor material in the via cavities can have a doping of a lesser concentration, thereby effectively increasing the distance between two steep junctions at edges of a source region and a drain region. Optionally, embedded active regions for additional devices can be formed prior to formation of the contiguous dielectric material layer. Raised active regions contacting a top surface of a substrate can be formed simultaneously with formation of the elevated active regions that are vertically spaced from the top surface.

First claim

The invention claimed is:

1. A semiconductor structure comprising:
a gate dielectric and a gate electrode overlying a channel of a first field effect transistor, wherein the channel comprises a surface portion of a first doped semiconductor well having a doping of a first conductivity type throughout and having a top surface located within a horizontal plane;
a gate spacer laterally surrounding the gate electrode;
a contiguous dielectric material layer laterally surrounding the gate electrode;
a first source-side via cavity extending from a bottom surface of the contiguous dielectric material layer to a top surface of the contiguous dielectric material layer and adjoined to the top surface of the first doped semiconductor well;
a first drain-side via cavity extending from the bottom surface of the contiguous dielectric material layer to the top surface of the contiguous dielectric material layer and adjoined to the top surface of the first doped semiconductor well;
a first source-side epitaxial pillar structure located entirely within the first source-side via cavity, having a doping of a second conductivity type that is the opposite of the first conductivity type throughout, and including a first source region therein; and
a first drain-side epitaxial pillar structure located entirely within the first drain-side via cavity, having a doping of the second conductivity type throughout, and including a first drain region therein, wherein:
a first p-n junction is located between the channel and the first source-side epitaxial pillar structure;
a second p-n junction is located between the channel and the first drain-side epitaxial pillar structure;
the first p-n junction and the second p-n junction are located entirely above, and are vertically spaced from, the horizontal plane including the top surface of the first doped semiconductor well; and
a second field effect transistor that comprises:
a second doped semiconductor well located in the substrate;
a second gate stack comprising another gate dielectric and another gate electrode and overlying the second doped semiconductor well, the second doped semiconductor well comprising a channel of the second field effect transistor;
a second source-side via cavity extending from the bottom surface of the contiguous dielectric material layer to the top surface of the contiguous dielectric material layer;
a second drain-side via cavity extending from the bottom surface of the contiguous dielectric material layer to the top surface of the contiguous dielectric material layer;
a raised source region located within the second source-side via cavity; and
a raised drain region located within the second drain-side via cavity;

wherein:
a periphery of the first source-side via cavity that is in contact with the top surface of the first doped semiconductor well is laterally offset from the gate spacer by a first portion of the contiguous dielectric material layer which contacts an upper surface of the first doped semiconductor well;
a periphery of the first drain-side via cavity that is in contact with the top surface of the first doped semiconductor well is laterally offset from the gate spacer by a second portion of the contiguous dielectric material layer which contacts the upper surface of the first doped semiconductor well;
the gate electrode and the gate dielectric comprise a first gate stack overlying the first doped semiconductor well;
the raised source region is an entirety of a second source-side epitaxial pillar structure;
the raised drain region is an entirety of a second drain-side epitaxial pillar structure;
the first source-side epitaxial pillar structure and the first drain-side epitaxial pillar structure have a greater thickness than the second source-side epitaxial pillar structure and the second drain-side epitaxial pillar structure;
the first doped semiconductor well has a doping of a first conductivity type;
the first source region and the first drain region have a doping of a second conductivity type that is the opposite of the first conductivity type;
the raised source region and the raised drain region have a doping of the opposite conductivity type with respect to the second doped semiconductor well;
the first source-side epitaxial pillar structure comprises a first source-extension region contacting the bottom surface of the first source region;
the first drain-side epitaxial pillar structure comprises a first drain-extension region contacting the bottom surface of the first drain region;
the first source-extension region and the first drain-extension region have a doping of a same conductivity type as the first source region and the first drain region; and
a dopant concentration of the first source-extension region and the first drain-extension region is lower than a dopant concentration of the first source region and the first drain region.

2. The semiconductor structure of claim 1 , wherein:
a dopant concentration of the first source-extension region and the first drain-extension region is lower than a dopant concentration of the first source region and the first drain region.

3. The semiconductor structure of claim 1 , further comprising:
a first source-side metallic via structure located in the first source-side via cavity, overlying the first source-side epitaxial pillar structure, and having a top surface that is planar with the top surface of the contiguous dielectric material layer;
a first drain-side metallic via structure located in the first drain-side via cavity, overlying the first drain-side epitaxial pillar structure, and having a top surface that is planar with the top surface of the contiguous dielectric material layer;
a first source-side metal-semiconductor alloy portion contacting a top surface of the first source region and a bottom surface of the first source-side metallic via structure; and
a first drain-side metal-semiconductor alloy portion contacting a top surface of the first drain region and a bottom surface of the first drain-side metallic via structure;
wherein:
the first source region has a horizontal cross-sectional shape that is entirely contained within a horizontal cross-sectional shape of the first source-side metallic via structure; and
the first drain region has a horizontal cross-sectional shape that is entirely contained within a horizontal cross-sectional shape of the first drain-side metallic via structure.

4. The semiconductor structure of claim 1 , wherein a top surface of the first doped semiconductor well and the top surface of the second doped semiconductor well are located within a same horizontal plane.

5. The semiconductor structure of claim 1 , wherein the first source region, the first drain region, the raised source region, and the raised drain region comprise a same doped semiconductor material.

6. The semiconductor structure of claim 1 , further comprising:
an embedded source region embedded within the second doped semiconductor well, located underneath a top surface of the substrate, and contacting a bottom surface of the raised source region; and
an embedded drain region embedded within the second doped semiconductor well, located underneath the top surface of the substrate, and contacting a bottom surface of the raised drain region.

7. The semiconductor structure of claim 1 , wherein:
each of the raised source region and the raised drain region has a greater horizontal cross-sectional area than any horizontal cross-sectional area of the first source region or the first drain region; and
the first source region, the first drain region, the raised source region, and the raised drain region have a same composition.

8. The semiconductor structure of claim 1 , wherein the first field ef

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Nishikawa Masatoshi
• Inoue Akira
• Toyama Fumiaki

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D84/8316

  the IGFETs characterised by having gate sidewall spacers specially adapted for integration · CPC title

• H10D84/836

  comprising EDMOS · CPC title

• H10D30/608 Primary

  having non-planar bodies, e.g. having recessed gate electrodes · CPC title