3D non-volatile memory with metal silicide interconnect

Patent metadata

Field	Value
Publication number	US-9281317-B2
Application number	US-201414533576-A
Country	US
Kind code	B2
Filing date	Nov 5, 2014
Priority date	Nov 21, 2011
Publication date	Mar 8, 2016
Grant date	Mar 8, 2016

Abstract

A stacked non-volatile memory cell array include cell areas with rows of vertical columns of NAND cells, and an interconnect area, e.g., midway in the array and extending a length of the array. The interconnect area includes at least one metal silicide interconnect extending between insulation-filled slits, and does not include vertical columns of NAND cells. The metal silicide interconnect can route power and control signals from below the stack to above the stack. The metal silicide interconnect can also be formed in a peripheral region of the substrate. Contact structures can extend from a terraced portion of the interconnect to at least one upper metal layer, above the stack, to complete a conductive path from circuitry below the stack to the upper metal layer. Subarrays can be provided in a plane of the array without word line hook-up and transfer areas between the subarrays.

First claim

What is claimed is:

1. A passive device, comprising:
a substrate;
a stack on the substrate, the stack comprising alternating dielectric layers and conductive layers the conductive layers comprise a bottom conductive layer and one other conductive layer, and the stack comprises a plurality of vertically-extending holes filled with oxide-nitride-oxide layers;
an above-stack metal layer, above the stack;
a first contact structure which extends up from the bottom conductive layer to the above-stack metal layer; and
a second contact structure which extends up from the one other conductive layer to the above-stack metal layer, the bottom conductive layer and the one other conductive layer are conductive plates of a capacitor and are connected in parallel to the above-stack metal layer by the first contact structure and the second contact structure.

2. The passive device of claim 1 , further comprising:
a below-stack metal layer, below the stack;
a contact structure which extends from the below-stack metal layer to the above-stack metal layer; and
circuitry direct below the stack, connected to the below-stack metal layer.

3. The passive device of claim 1 , wherein:
the passive device is in a peripheral area of a 3D stacked non-volatile memory device, lateral of a cell area of the substrate; and
the cell area comprises rows of vertical columns of NAND cells.

4. The passive device of claim 1 , wherein:
the stack comprises a terraced portion at which the bottom conductive layer touches the first contact structure, and at which the one other conductive layer touches the second contact structure.

5. The passive device of claim 1 , wherein:
the conductive layers comprise metal silicide.

6. The passive device of claim 1 , wherein:
the stack comprises an insulation-filled slit which extends from a bottom of the stack to a top of the stack.

7. A passive device, comprising:
a substrate;
a stack on the substrate, the stack comprises alternating dielectric layers and conductive layers, and a plurality of vertically-extending holes filled with oxide-nitride-oxide layers;
an above-stack metal layer, above the stack; and
contact structures which extend up from the conductive layers to the above-stack metal layer, the conductive layers are conductive plates of a capacitor and are connected in parallel to the above-stack metal layer by the contact structures.

8. The passive device of claim 7 , wherein:
the stack comprises an insulation-filled slit which extends from a bottom of the stack to a top of the stack.

9. The passive device of claim 7 , wherein:
the passive device is in a peripheral area of a 3D stacked non-volatile memory device, lateral of a cell area of the substrate.

Assignees

• Sandisk Technologies Inc

Inventors

• Higashitani Masaaki
• Rabkin Peter

Classifications

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10D64/661

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671) · CPC title

• H01L29/4916

  Electricity · mapped topic

• G11C16/06

  Auxiliary circuits, e.g. for writing into memory · CPC title

• H01L2924/00

  Electricity · mapped topic