Three-dimensional semiconductor memory devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-11424259-B2
Application number	US-202017011051-A
Country	US
Kind code	B2
Filing date	Sep 3, 2020
Priority date	Nov 20, 2017
Publication date	Aug 23, 2022
Grant date	Aug 23, 2022

Abstract

Three-dimensional semiconductor memory devices and methods of fabricating the same are provided. A memory device may include a semiconductor layer including first and second regions, first vertical structures on the first region and extending in a first direction perpendicular to a top surface of the semiconductor layer, and second vertical structures on the second region and extending in the first direction. The first vertical structure may include a vertical semiconductor pattern extending in the first direction and in contact with the semiconductor layer, and a first data storage pattern surrounding the vertical semiconductor pattern. The second vertical structure may include an insulation structure extending in the first direction and in contact with the semiconductor layer, and a second data storage pattern surrounding the insulation structure.

First claim

What is claimed is:

1. A three-dimensional semiconductor memory device, comprising:
a substrate including a first region and a second region;
an electrode structure including electrodes vertically stacked on the substrate;
a plurality of first vertical structures extending into the electrode structure on the first region; and
a plurality of second vertical structures extending into the electrode structure on the second region,
wherein each of the first vertical structures comprises:
a vertical semiconductor pattern extending into the electrode structure; and
a first data storage pattern between the vertical semiconductor pattern and the electrode structure,

wherein each of the second vertical structures comprises:
an insulation structure extending into the electrode structure; and
a second data storage pattern between the insulation structure and the electrode structure,

wherein each first vertical structure comprises a first width, and each second vertical structure comprises a second width greater than the first width,
wherein bottom surfaces of the insulation structures are lower than bottom surfaces of the vertical semiconductor patterns and bottom surfaces of the second data storage patterns,
wherein the first data storage pattern of one of the first vertical structures comprises a first thickness on a sidewall of the vertical semiconductor pattern of the one of the first vertical structures,
wherein the second data storage pattern of one of the second vertical structures comprises a second thickness on the sidewall of the insulation structure of the one of the second vertical structures, and
wherein the second thickness is substantially equal to or less than the first thickness.

2. The device of claim 1 , wherein each of the first and second vertical structures comprises a tunnel insulation layer, a charge storage layer, and a blocking insulation layer that are sequentially stacked.

3. The device of claim 1 , wherein a thickness of one of the vertical semiconductor patterns is less than half a width of one of the insulation structures.

4. The device of claim 1 , wherein at least one of the insulation structures directly contacts the substrate.

5. A three-dimensional semiconductor memory device, comprising:
a semiconductor layer including a first region and a second region;
a plurality of first vertical structures on the first region and extending in a first direction perpendicular to a top surface of the semiconductor layer; and
a plurality of second vertical structures on the second region and extending in the first direction,
wherein each of the first vertical structures comprises:
a vertical semiconductor pattern extending in the first direction and contacting the semiconductor layer; and
a first data storage pattern surrounding a periphery of the vertical semiconductor pattern, and

wherein each of the second vertical structures comprises:
an insulation structure extending in the first direction and contacting the semiconductor layer;
a second data storage pattern surrounding a periphery of the insulation structure; and
a protruding portion extending in the first direction and in a second direction perpendicular to the first direction.

6. The device of claim 5 , further comprising an electrode structure including electrodes vertically stacked on the semiconductor layer, wherein the electrode structure comprises a stepwise structure on the second region, wherein each of the electrodes comprises a pad that constitutes the stepwise structure on the second region, and wherein the second vertical structures extend into the pad of each of the electrodes.

7. The device of claim 6 , further comprising cell contact plugs coupled to the pads of the electrodes on the second region, wherein each of the cell contact plugs is between adjacent second vertical structures.

8. The device of claim 7 , wherein each of the cell contact plugs is partially surrounded by the second vertical structures, in a plan view.

9. A three-dimensional semiconductor memory device, comprising:
a substrate including a first region and a second region;
an electrode structure including electrodes vertically stacked on the substrate;
a plurality of first vertical structures extending into the electrode structure on the first region; and
a plurality of second vertical structures extending into the electrode structure on the second region,
wherein each of the first vertical structures comprises:
a vertical semiconductor pattern extending into the electrode structure;
a first data storage pattern between the vertical semiconductor pattern and the electrode structure; and
a first lower pattern in contact with the vertical semiconductor pattern, the first data storage pattern, and the substrate,

wherein each of the second vertical structures comprises:
an insulation structure extending into the electrode structure;
a second data storage pattern between the insulation structure and the electrode structure; and
a second lower pattern in contact with the insulating structure, the second data storage pattern, and the substrate, and

wherein each first lower pattern comprises a first width, and each second lower pattern comprises a second width greater than the first width.

10. The device of claim 9 , wherein the first data storage pattern of one of the first vertical structures comprises a first thickness on a sidewall of the vertical semiconductor pattern of the one of the first vertical structures,
wherein the second data storage pattern of one of the second vertical structures comprises a second thickness on the sidewall of the insulation structure of the one of the second vertical structures, and
wherein the second thickness is substantially equal to or less than the first thickness.

11. The device of claim 9 , wherein each of the first and second vertical structures comprises a tunnel insulation layer, a charge storage layer, and a blocking insulation layer that are sequentially stacked.

12. The device of claim 9 , wherein the first lower pattern and the second lower pattern are epitaxial patterns.

13. The device of claim 12 , wherein the first lower pattern has a first height and the second lower pattern has a second height that is less than the first height.

14. The device of claim 9 , further comprising an interlayer dielectric layer in contact with an upper surface of the insulation structures of the second vertical structures.

15. The device of claim 9 , wherein each first vertical structure comprises a bit line pad that is surrounded by the first data storage pattern.

16. The device of claim 15 , wherein each bit line pad is coupled to a bit line contact plug.

17. The device of claim 15 , wherein an upper surface of each bit line pad is substantially coplanar with upper surfaces of each insulation structure of the second vertical structures.

18. The device of claim 9 , further comprising a buffer insulation layer interposed between the substrate and the electrode structure.

19. The device of claim 9 , wherein the electrode structure has a stepwise structure on the second region.

20. The device of claim 19 , wherein each of the electrodes comprises a pad that constitutes the stepwise structure on the second region.

Assignees

• Samsung Electronics Co Ltd

Inventors

• JUNG Euntaek
• Shin Joongshik

Classifications

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D62/292

  Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512) · CPC title

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H01L29/7926

  Electricity · mapped topic