Multilevel memory stack structure employing support pillar structures

Patent metadata

Field	Value
Publication number	US-9627403-B2
Application number	US-201514862916-A
Country	US
Kind code	B2
Filing date	Sep 23, 2015
Priority date	Apr 30, 2015
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A first stack of alternating layers including first electrically insulating layers and first sacrificial material layers is formed with first stepped surfaces. First memory openings can be formed in a device region outside of the first stepped surfaces, and first support openings can be formed through the first stepped surfaces. The first memory openings and the first support openings can be filled with a sacrificial fill material. A second stack of alternating layers including second electrically insulating layers and second sacrificial material layers can be formed over the first stack. Inter-stack memory openings including the first memory openings can be formed in the device region, and inter-stack support openings including the first support openings can be formed in a steppes surface region. Memory stack structures and support pillar structure are simultaneously formed in the inter-stack memory openings and the inter-stack support openings, respectively.

First claim

What is claimed is:

1. A monolithic three-dimensional memory device comprising:
a lower stack structure comprising a first stack of alternating layers including first electrically insulating layers and first electrically conductive layers and located over a substrate;
an upper stack structure comprising a second stack of alternating layers including second electrically insulating layers and second electrically conductive layers and located over the lower stack structure;
an etch stop dielectric layer located within the lower stack structure and overlying the first stack of alternating layers and contacting a bottom surface of the upper stack structure and comprising a dielectric material having a different composition than the first electrically insulating layers;
a plurality of memory stack structures including respective vertical semiconductor channels, wherein a bottommost portion of each vertical semiconductor channel is electrically shorted to a source region located below the lower stack, and an upper portion of each vertical semiconductor channel is electrically shorted to a drain contact via structure overlying the vertical semiconductor channel; and
at least one support pillar structure located within a stepped surface region of the lower and upper stack structures, comprising a same set of materials as the plurality of memory stack structures.

2. The monolithic three-dimensional memory device of claim 1 , wherein:
an entire top surface of each of the at least one support pillar structure is in physical contact with a bottom surface of a dielectric material layer that overlies the at least one support pillar structure;
each of the plurality of memory stack structures comprises a memory film including a memory material layer and a tunneling dielectric layer.

3. The monolithic three-dimensional memory device of claim 2 , wherein:
each of the at least one support pillar structure comprises a dummy semiconductor channel having a same composition as, and a same thickness as, the semiconductor channel; and
the dummy semiconductor channel is not electrically connected to a driver circuit of the monolithic three-dimensional memory device.

4. The monolithic three-dimensional memory device of claim 3 , wherein:
each of the at least one support pillar structure comprises a dummy memory film including a dummy memory material layer having a same composition as, and a same thickness as, the memory film; and
each of the at least one support pillar structure comprises a dummy tunneling dielectric layer having a same composition as, and a same thickness as, the tunneling dielectric layer.

5. The monolithic three-dimensional memory device of claim 4 , wherein:
no charge is stored in the dummy memory film during operation of the monolithic three-dimensional memory device;
no charge carriers tunnel through the dummy tunneling dielectric layer during operation of the monolithic three-dimensional memory device; and
no current flows through the dummy semiconductor channel during operation of the monolithic three-dimensional memory device.

6. The monolithic three-dimensional memory device of claim 4 , wherein each of the plurality of memory stack structures comprises a drain region contacting an upper portion of a respective semiconductor channel and contacting a portion of a bottom surface of the dielectric material layer.

7. The monolithic three-dimensional memory device of claim 6 , wherein:
each of the at least one support pillar structure comprises a dummy drain region having a same composition as, and a same height as, the drain regions;
a respective drain contact via structure contacts each respective drain region; and
no drain contact via or another conductive structure contacts the dummy drain region.

8. The monolithic three-dimensional memory device of claim 1 , wherein:
each second electrically conductive layer that underlies at least another second electrically conductive layer laterally extends farther than any overlying layer among the second electrically conductive layers; and
each first electrically conductive layer that underlies at least another first electrically conductive layer laterally extends farther than any overlying layer among the first electrically conductive layers.

9. The monolithic three-dimensional memory device of claim 8 , further comprising control gate contact via structures located within the stepped surface region, vertically extending at least through a dielectric material portion within the upper stack structure, and contacting a respective electrically conductive layer selected from the first and second electrically conductive layers;
wherein:
the at least one support pillar structure comprises a plurality of support pillar structures; and
a nearest neighbor lateral distance for the plurality of support pillar structures is greater than a nearest neighbor distance among the plurality of memory stack structures.

10. The monolithic three-dimensional memory device of claim 1 , further comprising a backside contact via structure located within a backside contact trench which extends through the lower and the upper stack structures;
wherein:
the backside contact via structure is in contact with the source region;
the plurality of memory stack structures are located in respective memory openings having a notch in their sidewall;
the at least one support pillar structure is located in inter-stack support opening having a notch in its sidewall; and
the backside contract trench does not have a notch in its sidewall.

11. The monolithic three-dimensional memory device of claim 1 , wherein:
the lower stack structure further comprises a first dielectric material portion located on, and over, first stepped surfaces of the first stack;
the upper stack structure further comprises a second dielectric material portion located on, and over, second stepped surfaces of the second stack;
the first stepped surfaces and the second stepped surfaces are located within the stepped surface region; and
a subset of control gate contact via structures extends through the first dielectric material portion and the second dielectric material portion.

12. The monolithic three-dimensional memory device of claim 1 , wherein:
a bottommost portion of each vertical semiconductor channel is electrically shorted to the source region which is located within the substrate, and a topmost portion of each vertical semiconductor channel is electrically shorted to the drain contact via structure overlying the vertical semiconductor channel; and
each vertical semiconductor channel within the plurality of memory stack structures contacts a first semiconductor material portion having a doping of a first conductivity and located within the substrate.

13. The monolithic three-dimensional memory device of claim 1 , wherein:
the monolithic three-dimensional memory structure comprises a monolithic three-dimensional NAND memory device;
the first and second electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Liu Jin
• Zhang Tong
• Pachamuthu Jayavel
• Lee Yao-Sheng
• Alsmeier Johann

Classifications

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H01L27/11526

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic