Vertical memory devices having dummy channel regions

Patent metadata

Field	Value
Publication number	US-9716104-B2
Application number	US-201614987835-A
Country	US
Kind code	B2
Filing date	Jan 5, 2016
Priority date	Aug 7, 2015
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate;
a gate electrode layer structure that includes a plurality of spaced-apart gate electrode layers stacked on an upper surface of the semiconductor substrate;
a plurality of channel regions penetrating the gate electrode layers;
a plurality of dummy channel regions penetrating at least the lowermost of the gate electrode layers; and
a substrate insulating layer between the semiconductor substrate and the dummy channel regions.

2. The semiconductor device of claim 1 , wherein the substrate insulating layer comprises a plurality of substrate insulating patterns, wherein the semiconductor substrate includes a plurality of recesses, and wherein the substrate insulating patterns are formed in respective ones of the recesses.

3. The semiconductor device of claim 1 , wherein the dummy channel regions extend below the upper surface of the semiconductor substrate and directly contact the substrate insulating layer.

4. The semiconductor device of claim 1 , wherein the dummy channel regions comprise respective annular channel regions that penetrate a lowermost one of the gate electrode layers.

5. The semiconductor device of claim 4 , wherein the channel regions comprise respective epitaxial patterns on the semiconductor substrate and respective annular channel regions on upper surfaces of the respective epitaxial patterns.

6. The semiconductor device of claim 5 , wherein the epitaxial patterns penetrate a lowermost one of the gate electrode layers.

7. The semiconductor device of claim 1 , further comprising a plurality of bit lines, wherein the channel regions are electrically connected to respective ones of the bit lines and wherein the dummy channel regions are not electrically connected to any of the bit lines.

8. The semiconductor device of claim 1 , wherein the dummy channel regions penetrate a first region of the gate electrode layer structure that has a stepped structure, and wherein the channel regions are spaced-apart from the first region of the gate electrode layer structure.

9. A semiconductor device, comprising:
a semiconductor substrate having an upper surface that defines a horizontal plane;
a gate electrode layer structure that includes a plurality of gate electrode layers and a plurality of insulating layers that are alternately stacked in a vertical direction on the upper surface of the semiconductor substrate;
a plurality of dummy channel regions that penetrate the gate electrode layer structure, the dummy channel regions comprising respective annular channel layers that penetrate a lowermost of the gate electrode layers; and
a plurality of channel regions that penetrate the gate electrode layer structure, the channel regions comprising respective epitaxial patterns on the semiconductor substrate and respective annular channel regions on an upper surface of the respective epitaxial patterns,
wherein the dummy channel regions are spaced apart from the semiconductor substrate.

10. The semiconductor device of claim 9 , wherein bottom surfaces of the respective dummy channel regions extend below a bottom surface of the gate electrode layer structure.

11. The semiconductor device of claim 10 , further comprising a substrate insulating layer that includes a plurality of substrate insulating patterns that are provided in respective recesses in the upper surface of the semiconductor substrate.

12. The semiconductor device of claim 11 , wherein bottom surfaces of the respective dummy channel regions directly contact the substrate insulating layer.

13. The semiconductor device of claim 9 , wherein the channel regions comprise respective epitaxial patterns on the semiconductor substrate and respective annular channel regions on upper surfaces of the respective epitaxial patterns.

14. The semiconductor device of claim 13 , wherein the epitaxial patterns of the respective channel regions penetrate a lowermost one of the gate electrode layers.

15. The semiconductor device of claim 9 , further comprising a plurality of bit lines, wherein the channel regions are electrically connected to respective ones of the bit lines and wherein the dummy channel regions are not electrically connected to any of the bit lines.

16. A semiconductor memory device, comprising:
a semiconductor substrate having an upper surface that has a plurality of recesses therein;
a substrate insulating layer that includes a plurality of substrate insulating patterns in the respective recesses;
a gate electrode layer structure on the upper surface of the semiconductor substrate; and
a plurality of dummy channel regions vertically penetrating the gate electrode layer structure, wherein the dummy channel regions directly contact the substrate insulating layer.

17. The semiconductor device of claim 16 , wherein the dummy channel regions have respective lower surfaces that are below the upper surface of the semiconductor substrate.

18. The semiconductor device of claim 16 , further comprising a plurality of channel regions, the channel regions comprising respective epitaxial patterns on the semiconductor substrate and respective annular channel regions on upper surfaces of the respective epitaxial patterns.

19. The semiconductor device of claim 18 , wherein the epitaxial patterns directly contact the semiconductor substrate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jong Won
• Lim Seung Hyun
• Kang Chang Seok
• Park Young Woo
• Bae Dae Hoon
• Eun Dong Seog
• Lee Woo Sung
• Lee Jae Duk
• Lim Jae Woo
• Choi Hanmei

Classifications

• H01L27/11556

  Electricity · mapped topic

• H01L27/11568

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11521

  Electricity · mapped topic

• H10D62/40

  Crystalline structures · CPC title