Methods and apparatus for controlling warpage in wafer level packaging processes

Patent metadata

Field	Value
Publication number	US-11421316-B2
Application number	US-201916584695-A
Country	US
Kind code	B2
Filing date	Sep 26, 2019
Priority date	Oct 26, 2018
Publication date	Aug 23, 2022
Grant date	Aug 23, 2022

Abstract

Methods and apparatus for producing fine pitch patterning on a substrate. Warpage correction of the substrate is accomplished on a carrier or carrier-less substrate. A first warpage correction process is performed on the substrate by raising and holding a temperature of the substrate to a first temperature and cooling the carrier-less substrate to a second temperature. Further wafer level packaging processing is then performed such as forming vias in a polymer layer on the substrate. A second warpage correction process is then performed on the substrate by raising and holding a temperature of the substrate to a third temperature and cooling the substrate to a fourth temperature. With the warpage of the substrate reduced, a redistribution layer may be formed on the substrate with a 2/2 μm l/s fine pitch patterning.

First claim

The invention claimed is:

1. A method of fine pitch patterning on a substrate in a wafer level packaging process, comprising:
performing a first warpage correction process on the substrate by ramping to and holding the substrate at a first temperature for a first duration and ramping to and holding a second temperature for a second duration, wherein the first temperature is greater than the second temperature;
forming vias in a polymer layer on the substrate;
curing the polymer layer;
performing a second warpage correction process on the substrate by ramping to and holding the substrate at a third temperature for a third duration and ramping to and holding the substrate at a fourth temperature for a fourth duration, wherein the third temperature is greater than the fourth temperature; and
forming a redistribution layer on the substrate with a fine pitch patterning having a line/space of 10/10 μm or less.

2. The method of claim 1 , wherein the fine pitch patterning has a line/space of 5/5 μm or less.

3. The method of claim 1 , wherein the fine pitch patterning has a line/space of 2/2 μm or less.

4. The method of claim 1 , wherein the substrate has a warpage of 500 μm or less after the second warpage correction process.

5. The method of claim 4 , wherein the substrate has a warpage of 400 μm or less after the second warpage correction process.

6. The method of claim 1 , wherein the first temperature of the first warpage correction process is greater than the third temperature of the second warpage correction process.

7. The method of claim 1 , wherein the first temperature of the first warpage correction process is approximately equal to the third temperature of the second warpage correction process.

8. The method of claim 1 , wherein the first temperature is adjusted prior to performing additional warpage correction processes to increase warpage correction performance.

9. The method of claim 1 , wherein the first temperature is approximately a glass transition temperature of the polymer layer on the substrate.

10. The method of claim 1 , wherein the first temperature, the second temperature, the third temperature, or the fourth temperature is obtained by ramping linearly.

11. The method of claim 1 , wherein the first temperature is lower than a glass transition temperature of the polymer layer when a plasma vapor deposition (PVD) process has been performed prior to the first warpage correction process.

12. The method of claim 1 , wherein the substrate is a reconstituted wafer composed of multiple dies.

13. The method of claim 1 , further comprising:
performing a chemical mechanical polishing (CMP) process to enhance the fine pitch patterning.

14. A non-transitory, computer readable medium having instructions stored thereon that, when executed, cause a method of fine pitch patterning on a substrate in a wafer level packaging process to be performed, the method comprising:
performing a first warpage correction process on the substrate by ramping to and holding the substrate at a first temperature for a first duration and ramping to and holding a second temperature for a second duration, wherein the first temperature is greater than the second temperature;
forming vias in a polymer layer on the substrate;
curing the polymer layer;
performing a second warpage correction process on the substrate by ramping to and holding the substrate at a third temperature for a third duration and ramping to and holding the substrate at a fourth temperature for a fourth duration, wherein the third temperature is greater than the fourth temperature; and
forming a redistribution layer on the substrate with a fine pitch patterning having a line/space of 10/10 μm or less.

15. The non-transitory, computer readable medium of claim 14 , wherein the first temperature of the first warpage correction process is greater than the third temperature of the second warpage correction process, wherein the substrate has a warpage of 400 μm or less after the second warpage correction process, and wherein the fine pitch patterning has a line/space is 2/2 μm or less.

Assignees

• Applied Materials Inc

Inventors

• Lianto Prayudi
• Rafi Mohamed
• Sulaiman Muhammad Azim Bin Syed
• See Guan Huei
• Kristy Ang Yu Xin
• Elumalai Karthik
• Thirunavukarasu Sriskantharajah
• Sundarrajan Arvind

Classifications

• H10P72/0616 Primary

  Monitoring of warpages, curvatures, damages, defects or the like · CPC title

• H10P72/0602

  Temperature monitoring · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W72/90

  Bond pads, in general · CPC title