Semiconductor devices

Patent metadata

Field	Value
Publication number	US-11417776-B2
Application number	US-201916715431-A
Country	US
Kind code	B2
Filing date	Dec 16, 2019
Priority date	May 30, 2019
Publication date	Aug 16, 2022
Grant date	Aug 16, 2022

Abstract

A semiconductor device, including a silicon on insulator (SOI) substrate is disclosed. The device may include gate structures formed on the SOI substrate and being spaced apart from each other in a horizontal direction, and a plurality of channels spaced apart from each other in a vertical direction. Each of the channels may extend through each of the gate structures in the horizontal direction. The device may include a seed layer and a source/drain region. The source/drain region may be connected to the channels, and each sidewall of the source/drain region in the horizontal direction may have a concave-convex shape. The device may include a protruding portion of the source/drain region formed between the gate structures that protrudes in the horizontal direction compared to a non-protruding portion of the source/drain region formed between the channels.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate having a recess formed in a non-oxidized upper portion thereof;
gate structures formed on the substrate and being spaced apart from each other in a horizontal direction that is substantially parallel to an upper surface of the substrate;
a plurality of channels spaced apart from each other in a vertical direction substantially perpendicular to the upper surface of the substrate, each of the channels extending through each of the gate structures in the horizontal direction;
a seed layer in the recess; and
a source/drain region on the seed layer, the source/drain region connected to the channels,
wherein each sidewall of the source/drain region in the horizontal direction has a concave-convex shape,
wherein a protruding portion of the source/drain region formed between a pair of the gate structures located at the same level above the substrate in the vertical direction, protrudes in the horizontal direction compared to a non-protruding portion of the source/drain region formed between the channels,
wherein the plurality of channels include a first channel at a lowermost level, a second channel at a middle level, and a third channel at an uppermost level, and
wherein an upper surface of the third channel has a greater length in the horizontal direction than a lower surface thereof.

2. The semiconductor device of claim 1 ,
wherein the source/drain region is widest in the horizontal direction at a portion formed at a height between the first and second channels.

3. The semiconductor device of claim 1 , wherein an upper surface of the second channel has substantially the same length in the horizontal direction as a lower surface thereof.

4. The semiconductor device of claim 1 , wherein an upper surface of the first channel has a smaller length in the horizontal direction than a lower surface thereof.

5. The semiconductor device of claim 1 , wherein at least a central portion of an upper surface of the seed layer is flat in the horizontal direction.

6. The semiconductor device of claim 5 , wherein the upper surface of the seed layer is flat.

7. The semiconductor device of claim 1 , wherein an upper surface of the seed layer is concave.

8. The semiconductor device of claim 1 , wherein a lower surface of the seed layer is downwardly convex.

9. The semiconductor device of claim 1 , wherein a height of an upper surface of the seed layer is lower than that of a lower surface of each of the gate structures.

10. The semiconductor device of claim 1 , wherein the source/drain region includes silicon-germanium doped with impurities.

11. A semiconductor device, comprising:
a substrate having a recess formed in a non-oxidized upper portion thereof;
gate structures formed on the substrate and being spaced apart from each other;
a plurality of channels spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, each of the channels extending through each of the gate structures in a horizontal direction substantially parallel to the upper surface of the substrate;
a seed layer in the recess, the seed layer having a lower surface that is downwardly convex and including silicon-germanium; and
a source/drain region on the seed layer, the source/drain region being connected to the channels,
wherein the channels include a first channel at a lowermost level, a second channel at a middle level, and a third channel at an uppermost level in each of the gate structures, and
wherein an upper surface of the third channel has a greater length in the horizontal direction than a lower surface thereof.

12. The semiconductor device of claim 11 , wherein at least a central portion of an upper surface of the seed layer is flat.

13. The semiconductor device of claim 11 , wherein each of both sidewalls of the source/drain region in the horizontal direction has a concave-convex shape.

14. The semiconductor device of claim 13 , wherein a protruding portion of the source/drain region formed between the gate structures protrudes in the horizontal direction compared to a non-protruding portion of the source/drain region formed between the channels.

15. The semiconductor device of claim 14 ,
wherein the source/drain region is widest in the horizontal direction at a portion formed at a height between the first and second channels.

16. A semiconductor device, comprising:
a substrate having a recess formed in a non-oxidized upper portion thereof;
gate structures formed on the substrate and being spaced apart from each other in a horizontal direction substantially parallel to an upper surface of the substrate;
a plurality of channels spaced apart from each other in a vertical direction substantially perpendicular to the upper surface of the substrate, each of the channels extending through each of the gate structures in the horizontal direction;
a seed layer in the recess, the seed layer including silicon-germanium; and
a source/drain region on the seed layer, the source/drain region being connected to the channels and having a variable width in the horizontal direction that varies along the vertical direction,
wherein the plurality of channels include a first channel at a lowermost level, a second channel at a middle level, and a third channel at an uppermost level, and
wherein an upper surface of the third channel has a greater length in the horizontal direction than a lower surface thereof.

17. The semiconductor device of claim 16 , wherein a first width of a first portion of the source/drain region formed between a first pair of gate structures spaced apart from each other in the horizontal direction and located at the same level in the vertical direction is different from a second width of a second portion of the source/drain region formed between a second pair of gate structures spaced apart from each other in the horizontal direction and located at the same level in the vertical direction, and
wherein the first width of the first portion of the source/drain region and the second width of the second portion of the source/drain region are greater than a width of a portion of the source/drain region formed between the channels.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Sujin
• Park Junbeom
• Kim Kihwan
• Jang Sunguk
• Cho Youngdae

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/274

  using seed materials · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D84/013

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title