Integration methods to fabricate internal spacers for nanowire devices
US-2017053998-A1 · Feb 23, 2017 · US
Stacked nanowire semiconductor device
US2017194429A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2017194429-A1 |
| Application number | US-201615177483-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jun 9, 2016 |
| Priority date | Jan 5, 2016 |
| Publication date | Jul 6, 2017 |
| Grant date | — |
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Abstract
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A method for forming a semiconductor device comprising forming a stack of nanowires, the stack including a first nanowire having a first length, and a second nanowire having a second length, the second nanowire arranged above the first nanowire, forming a sacrificial gate stack on the stack of nanowires, growing a source/drain region on the first, second nanowires, removing the sacrificial gate stack to expose channel regions of the first and second nanowires, and forming a gate stack over the channel regions.
First claim
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1 . A semiconductor device comprising: a stack of nanowires, the stack including: a first nanowire having a first length; a second nanowire having a second length, the second nanowire arranged above the first nanowire; and a third nanowire having a third length, the third nanowire arranged above the second nanowire; and a gate stack arranged over channel regions of the first nanowire, the second nanowire, and the third nanowire; a source/drain region encapsulating the first, second, and third nanowires, such that the source/drain region is in between the first, second, and third nanowires. 2 . The device of claim 1 , wherein the first nanowire has a length greater than a length of the second nanowire. 3 . (canceled) 4 . The device of claim 1 , wherein the second nanowire has a length greater than a length of the third nanowire. 5 . (canceled) 6 . The device of claim 1 , wherein: the source/drain region is arranged on the first nanowire; the source/drain region is arranged on the second nanowire; and the source/drain region is arranged on the third nanowire. 7 . The device of claim 1 , wherein the first nanowire, the second nanowire, and the third nanowire include a semiconductor material.
Assignees
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Classifications
Silicon, silicon germanium or germanium · CPC title
- H01L29/0673Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Complementary IGFETs, e.g. CMOS · CPC title
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- What does patent US2017194429A1 cover?
- A method for forming a semiconductor device comprising forming a stack of nanowires, the stack including a first nanowire having a first length, and a second nanowire having a second length, the second nanowire arranged above the first nanowire, forming a sacrificial gate stack on the stack of nanowires, growing a source/drain region on the first, second nanowires, removing the sacrificial gate…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H01L29/0673. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Jul 06 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).