Gate all around device structure and Fin field effect transistor (FinFET) device structure

Patent metadata

Field	Value
Publication number	US-9620607-B2
Application number	US-201414560644-A
Country	US
Kind code	B2
Filing date	Dec 4, 2014
Priority date	Dec 4, 2014
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

A gate all around (GAA) device structure, vertical gate all around (VGAA) device structure, horizontal gate all around (HGAA) device structure and fin field effect transistor (FinFET) device structure are provided. The VGAA device structure includes a substrate and an isolation structure formed in the substrate. The VGAA device structure also includes a first transistor structure formed on the substrate, and the first transistor structure includes a vertical structure. The vertical structure includes a source region, a channel region and a drain region, and the channel region is formed between the source region and the drain region. The channel region has a horizontal portion and a sloped portion sloping downward toward the isolation structure. The VGAA device structure further includes a gate stack structure wrapping around the channel region.

First claim

What is claimed is:

1. A vertical gate all around (GAA) device structure, comprising:
a substrate;
an isolation structure formed in the substrate;
a first transistor structure formed on the substrate, wherein the first transistor structure comprises a vertical structure, and the vertical structure comprises a source region, a channel region and a drain region, and wherein the channel region is formed between the source region and the drain region, and the channel region has a horizontal portion and a sloped portion sloping downward toward the isolation structure, the sloped portion comprises a first sidewall sloping downward toward the isolation structure and adjoining the source region and a second sidewall sloping downward toward the isolation structure and adjoining the drain region, the first sidewall is spaced apart from the second sidewall, and the first sidewall and the second sidewall overlap from a top view of the vertical gate all around (GAA) device structure; and
a gate stack structure wrapping around the channel region.

2. The vertical gate all around (GAA) device structure as claimed in claim 1 , wherein a first distance between the horizontal portion of the channel region and the substrate is greater than a second distance between the sloped portion of the channel region and the substrate.

3. The vertical gate all around (GAA) device structure as claimed in claim 1 , wherein the vertical structure has a circular shape, a bar-like shape when seen from a top-view.

4. The vertical gate all around (GAA) device structure as claimed in claim 1 , wherein the source region has a horizontal portion and a sloped downward portion.

5. The vertical gate all around (GAA) device structure as claimed in claim 1 , wherein the drain region has a horizontal portion and a sloped portion.

6. The vertical gate all around (GAA) device structure as claimed in claim 1 , wherein the gate stack structure comprises a high-k dielectric layer and a metal gate electrode.

7. The vertical gate all around (GAA) device structure as claimed in claim 1 , further comprising:
a second transistor structure formed on the substrate, wherein the isolation structure is formed between the first transistor structure and the second transistor structure, and wherein
the second transistor structure comprises a second vertical structure, and the second vertical structure comprises a source region, a channel region and a drain region, and wherein the channel region of the second transistor structure is formed between the source region and the drain region, and wherein the channel region of the second transistor structure has a horizontal portion and a downward-sloping portion.

8. The vertical gate all around (GAA) device structure as claimed in claim 7 , wherein the first transistor structure is a PMOS transistor structure and the second transistor structure is a NMOS transistor structure.

9. The vertical gate all around (GAA) device structure as claimed in claim 1 , wherein the source region is made of a first epitaxial material, the channel region is made of a second epitaxial material, and the drain region is made of a third epitaxial material.

10. The vertical gate all around (GAA) device structure as claimed in claim 9 , wherein the first epitaxial material, the second epitaxial material and the third epitaxial material each independently comprises Si, Ge, SiGe, SiC, InSb, InAs, GaAs, GaSb, InGaSb, InGaAs, or combinations thereof.

11. The vertical gate all around (GAA) device structure as claimed in claim 1 , further comprising:
gate spacers formed between the source region and the gate stack structure or between the drain region and the gate stack structure.

12. The vertical gate all around (GAA) device structure as claimed in claim 7 , further comprising:
an ILD layer formed over the isolation structure and between the first transistor structure and the second transistor structure.

13. The vertical gate all around (GAA) device structure as claimed in claim 1 , further comprising:
a well region formed in the substrate, wherein the first transistor structure is formed on the well region.

14. A vertical gate all around (GAA) device structure, comprising:
a substrate;
an isolation structure formed in the substrate;
an ILD layer formed over the isolation structure;
a vertical structure formed on the substrate, wherein the vertical structure comprises a sloped region which is sloping downward toward the isolation structure, and the sloped region is in direct contact with the ILD layer; and
a gate stack structure adjoining a portion of the sloped region.

15. The vertical gate all around (GAA) device structure as claimed in claim 14 , wherein the sloped region is not parallel to a top surface of the isolation structure.

16. The vertical gate all around (GAA) device structure as claimed in claim 14 , wherein the sloped region is higher than a top surface of the isolation structure.

17. The vertical gate all around (GAA) device structure as claimed in claim 14 , further comprising:
a gate spacer formed over the isolation structure.

18. A vertical gate all around (GAA) device structure, comprising:
a substrate;
a first vertical structure formed on the substrate;
a second vertical structure formed on the substrate;
an isolation structure formed in the substrate, wherein the isolation structure is formed between the first vertical structure and the second vertical structure, the first vertical structure comprise a first sloped region toward the isolation structure, the second vertical structure comprise a second sloped region far away from the isolation structure, the first sloped portion comprises a first sidewall sloping downward toward the isolation structure and adjoining the source region and a second sidewall sloping downward toward the isolation structure and adjoining the drain region, the first sidewall is spaced apart from the second sidewall, and the first sidewall and the second sidewall overlap from a top view of the vertical gate all around (GAA) device structure;
a first gate stack structure wrapping around the first sloped region; and
a second gate stack structure wrapping around the second sloped region.

19. The vertical gate all around (GAA) device structure as claimed in claim 18 , wherein the first vertical structure further comprises a source region and a drain region, and the first sloped region is formed between the source region and the drain region.

20. The vertical gate all around (GAA) device structure as claimed in claim 18 , wherein the substrate comprise a lower portion and an upper portion, the second vertical structure is formed on the lower portion and the second sloped region sloping downward toward the upper portion.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Yu-Lien
• Wang Chin-Chi

Classifications

• H01L29/42356

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic

• H01L29/1033

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic

• H01L29/42392 Primary

  Electricity · mapped topic