Methods of forming microelectronic devices and memory devices, and related microelectronic devices, memory devices, and electronic systems

Patent metadata

Field	Value
Publication number	US-11417676-B2
Application number	US-202017000754-A
Country	US
Kind code	B2
Filing date	Aug 24, 2020
Priority date	Aug 24, 2020
Publication date	Aug 16, 2022
Grant date	Aug 16, 2022

Abstract

A method of forming a microelectronic device comprises forming a memory array region comprising memory cells vertically over a base structure comprising a semiconductive material and alignment mark structures vertically extending into the semiconductive material. First contact structures are formed to extend through the memory array region and into the alignment mark structures. A support structure is formed over the memory array region. A portion of the base structure is removed to expose the alignment mark structures. A control logic region is formed vertically adjacent a remaining portion of the base structure. The control logic region comprises control logic devices in electrical communication with the first contact structures by way of second contact structures extending partially through the alignment mark structures and contacting the first contact structures. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.

First claim

What is claimed is:

1. A method of forming a microelectronic device, comprising:
forming a memory array region comprising memory cells vertically over a base structure comprising a semiconductive material and alignment mark structures vertically extending into the semiconductive material;
forming first contact structures vertically extending through the memory array region and into the alignment mark structures of the base structure;
forming a support structure over the memory array region;
removing a portion of the base structure to expose the alignment mark structures after forming the support structure over the memory array region; and
forming a control logic region vertically adjacent a remaining portion of the base structure, the control logic region comprising control logic devices in electrical communication with the first contact structures by way of second contact structures vertically extending partially through the alignment mark structures and contacting the first contact structures.

2. The method of claim 1 , further comprising forming the base structure by:
forming trenches vertically extending into the semiconductive material; and
filling the trenches with at least one additional material to form the alignment mark structures.

3. The method of claim 1 , wherein forming first contact structures comprises:
forming vias vertically extending through the memory array region and partially into the alignment mark structures of the base structure; and
filling the vias with conductive material.

4. The method of claim 1 , wherein forming first contact structures comprises:
forming first vias vertically extending partially into the alignment mark structures of the base structure prior to forming the memory array region over the base structure;
filling the first vias with conductive material;
forming second vias vertically extending through the memory array region and exposing the conductive material filling the first vias; and
filling the second vias with additional conductive material.

5. The method of claim 1 , wherein forming a memory array region comprises forming the memory array region to further comprise:
a source structure;
a stack structure over the source structure and comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers;
cell pillar structures vertically extending through stack structure and in electrical communication with the source structure, portions of the cell pillar structures and the conductive structures of the stack structure forming vertically extending strings of the memory cells; and
a conductive routing tier overlying the stack structure and comprising:
digit line structures in electrical communication with the vertically extending strings of the memory cells; and
routing structures in electrical communication with the first contact structures.

6. The method of claim 5 , further comprising forming the memory array region to further comprise:
a staircase structure within the stack structure and having steps comprising horizontal ends of the tiers; and
third contact structures vertical extending from at least some of the steps of the staircase structure to at least some of the routing structures of the conductive routing tier.

7. The method of claim 5 , further comprising forming the source structure of the memory array region to vertically extend into the semiconductive material of the base structure.

8. The method of claim 1 , wherein forming a support structure over the memory array region comprises attaching a wafer structure above a conductive routing tier of the memory array region overlying the memory cells of the memory array region.

9. The method of claim 1 , wherein forming a support structure over the memory array region comprises depositing one or more of an insulative material and a semiconductive material above a conductive routing tier of the memory array region overlying the memory cells of the memory array region.

10. The method of claim 1 , wherein removing a portion of the base structure to expose the alignment mark structures comprises:
vertically inverting the base structure, the memory array region, and the support structure after forming the support structure over the memory array region; and
removing the semiconductive material of the base structure down to vertical boundaries of the alignment mark structures after the vertically inverting the base structure, the memory array region, and the support structure.

11. The method of claim 1 , wherein forming a control logic region vertically adjacent a remaining portion of the base structure comprises:
forming transistors at least partially vertically overlying the remaining portion of the base structure; and
forming routing structures vertically over and in electrical communication with the transistors, the transistors and the routing structures forming control logic circuitry of the control logic devices of the control logic region.

12. The method of claim 11 , wherein forming transistors comprises forming each of the transistors to individually comprise:
a source region within the remaining portion of the base structure;
a drain region within the remaining portion of the base structure;
a channel region within the remaining portion of the base structure and horizontally intervening between the source region and the drain region; and
a gate structure vertically overlying and at least partially horizontally overlapping the channel region.

13. The method of claim 11 , further comprising forming third conductive contact structures vertically extending between and coupling at least some of the routing structures and at least some of the transistors.

14. A microelectronic device, comprising:
a memory array region comprising memory cells;
a semiconductive structure overlying the memory array region and comprising alignment mark structures vertically extending through material of the semiconductive structure;
conductive contact structures vertically extending through the memory array region and partially into the alignment mark structures;
a control logic region partially overlying the semiconductive structure and comprising:
transistors; and
routing structures overlying and in electrical communication with the transistors; and

additional conductive contact structures vertically extending from some of the routing structures, partially through the alignment mark structures, and to the conductive contact structures.

15. The microelectronic device of claim 14 , wherein the memory array region comprises:
a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, each of the tiers including at least one of the conductive structures and at least one of the insulative structures;
cell pillar structures vertically extending through the stack structure, portions of the cell pillar structures and the conductive structures of the stack structure forming vertically extending strings of the memory cells;
a routing tier underlying the stack structure and comprising:
digit line structures in electrical communication with the cell pillar structures; and
additional routing structures in electrical communication with the conductive contact structures; and

at least one source structure overlying the stack structure and in electrical communication with the cell pillar structures.

16. The microelectronic device of claim 15 , wherein the memory array region further comprises:
an inverted staircase structure within the stack stru

Assignees

• Micron Technology Inc

Inventors

• Meotto Umberto Maria
• Camerlenghi Emilio
• Tessariol Paolo
• Laurin Luca

Classifications

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title