Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-11417601-B2
Application number	US-202016909968-A
Country	US
Kind code	B2
Filing date	Jun 23, 2020
Priority date	Jun 5, 2020
Publication date	Aug 16, 2022
Grant date	Aug 16, 2022

Abstract

A device includes a transistor, an insulating structure, a buried conductive line, and a buried via. The transistor is above a substrate and includes a source/drain region and a source/drain contact above the source/drain region. The insulating structure is above the substrate and laterally surrounds the transistor. The buried conductive line is in the insulating structure and spaced apart from the transistor. The buried via is in the insulating structure and interconnects the transistor and the buried conductive line. A height of the buried conductive line is greater than a height of the source/drain contact.

First claim

What is claimed is:

1. A device comprising:
a transistor above a substrate, wherein the transistor comprises:
a source/drain region; and
a source/drain contact above the source/drain region;

an insulating structure above the substrate and laterally surrounding the transistor;
a buried conductive line in the insulating structure and spaced apart from the transistor; and
a buried via in the insulating structure and interconnecting the transistor and the buried conductive line, wherein a height of the buried conductive line is greater than a height of the source/drain contact, and a top surface of the buried conductive line is substantially coplanar with a top surface of the buried via.

2. The device of claim 1 , wherein the source/drain contact is spaced apart from the buried conductive line.

3. The device of claim 1 , wherein the buried via is in direct contact with the buried conductive line and the source/drain contact.

4. The device of claim 2 , wherein a bottom surface of the buried conductive line is lower than a bottom surface of the source/drain contact.

5. The device of claim 2 , wherein the top surface of the buried conductive line is higher than a top surface of the source/drain contact.

6. The device of claim 1 , wherein the transistor further comprises a gate structure, and the buried via is in direct contact with the buried conductive line and the gate structure.

7. The device of claim 6 , wherein the gate structure and the buried conductive line extend in different directions.

8. The device of claim 1 , wherein the insulating structure comprises:
an isolation structure above the substrate; and
an interlayer dielectric above the isolation structure.

9. The device of claim 8 , wherein a bottom surface of the buried conductive line is lower than a top surface of the isolation structure.

10. The device of claim 8 , wherein the top surface of the buried conductive line and a top surface of the interlayer dielectric are substantially coplanar.

11. A device comprising:
a transistor above a substrate, wherein the transistor comprises source and drain regions, a channel between the source and drain regions, and a gate structure, and at least a portion of the gate structure of the transistor is directly above the channel of the transistor;
an insulating structure above the substrate and laterally surrounding the transistor, wherein the insulating structure comprises:
an isolation structure above the substrate; and
an interlayer dielectric above the isolation structure, and a portion of the interlayer dielectric is lower than the isolation structure;

a first conductive line above the insulating structure and the transistor, wherein a bottom surface of the first conductive line is higher than a top surface of the gate structure of the transistor; and
a second conductive line above the substrate and partially buried in the insulating structure, wherein the first and second conductive lines extend in a first direction, top surfaces of the first and second conductive lines are substantially coplanar, and a height of the second conductive line is greater than a height of the first conductive line.

12. The device of claim 11 , wherein a width of the second conductive line is not greater than a width of the first conductive line.

13. The device of claim 11 , wherein a bottom surface of the second conductive line is lower than a bottom surface of the insulating structure.

14. The device of claim 11 , further comprising a buried conductive line directly under the second conductive line, wherein the buried conductive line is adjacent the transistor.

15. The device of claim 11 , wherein the second conductive line extends into the interlayer dielectric of the insulating structure.

16. A method for manufacturing a device comprising:
forming a transistor above a substrate;
forming a first trench in the substrate;
forming an insulating structure above the substrate, surrounding the transistor, and partially in the first trench;
forming a second trench and a contact opening in the insulating structure, wherein the second trench does not expose the transistor, and the contact opening exposes a source/drain region of the transistor; and
after forming the second trench and the contact opening, filling the second trench and the contact opening with a conductive material to form a first buried conductive line in the second trench and adjacent the transistor, and to form a source/drain contact above the source/drain region of the transistor.

17. The method of claim 16 , wherein the first buried conductive line is directly formed above a portion of the insulating structure in the first trench.

18. The method of claim 16 , further comprising:
forming a first dielectric layer above the first buried conductive line; and
forming a power line above the first dielectric layer and directly above the first buried conductive line.

19. The method of claim 18 , further comprising:
forming a second dielectric layer above the first buried conductive line prior to forming the first dielectric layer; and
forming a second buried conductive line in the second dielectric layer and directly above the first buried conductive line.

20. The method of claim 16 , further comprising:
forming an opening in the insulating structure; and
forming a buried via in the insulating structure such that the buried via interconnects the first buried conductive line and the transistor.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Tsmc Nanjing Company Ltd
• Tsmc China Company Ltd

Inventors

• Wang xin-yong
• Han Liu
• Tien Li-Chun
• Chen Chih-Liang

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title