Gate driving unit circuit, gate driving circuit, display device and driving method for improving charge rate

Patent metadata

Field	Value
Publication number	US-11417261-B2
Application number	US-201916624102-A
Country	US
Kind code	B2
Filing date	Aug 6, 2019
Priority date	Sep 27, 2018
Publication date	Aug 16, 2022
Grant date	Aug 16, 2022

Abstract

A gate driving unit circuit comprises an input sub-circuit and an output sub-circuit. The input sub-circuit is connected to a first pull-up node, a second pull-up node, and an input terminal, and transmits a signal input from the input terminal to the first pull-up node and the second pull-up node. The output sub-circuit is connected to the first pull-up node, the second pull-up node, a first control terminal, a third control terminal, a first output terminal, and a second output terminal. The output sub-circuit transmits a signal input through the first control terminal to the first output terminal, and transmits a signal input through the third control terminal to the second output terminal under the control of a potential of the second pull-up node, wherein, an effective voltage of a signal of the first control terminal is greater than that of a signal of the third control terminal.

First claim

What is claimed is:

1. A gate driving unit circuit, being the gate driving unit circuit at a stage of a gate driving circuit comprising a plurality of cascaded gate driving unit circuits, and comprising an input sub-circuit, an output sub-circuit, and a pull-down node control sub-circuit, wherein:
the input sub-circuit is connected to a first pull-up node, a second pull-up node and an input terminal, and the input sub-circuit is configured to transmit a signal input from the input terminal to the first pull-up node and the second pull-up node;
the output sub-circuit is connected to the first pull-up node, the second pull-up node, a first control terminal, a third control terminal, a first output terminal and a second output terminal, and the output sub-circuit is configured to transmit a signal input through the third control terminal to the second output terminal under the control of a potential of the first pull-up node, and the output sub-circuit is configured to transmit a signal input through the first control terminal to the first output terminal under the control of a potential of the second pull-up node;
the pull-down node control sub-circuit is connected to the first pull-up node, the pull-down node, a first voltage terminal and a second control terminal and the pull-down node control sub-circuit is not connected to the second pull-up node, where the pull-down node control sub-circuit is configured to transmit a signal input from the second control terminal to the pull-down node under the control of the signal input from the second control terminal, and is configured to transmit a signal input from the first voltage terminal to the pull-down node under the control of the potential of the first pull-up node; and
the first control terminal and the third control terminal are configured to simultaneously input a signal to the output sub-circuit, and an effective voltage of the signal input from the first control terminal is greater than an effective voltage of the signal input from the third control terminal, so that the pull-down node control sub-circuit is turned on under the control of a lower voltage while the first output terminal of the output terminal circuit outputs a higher voltage.

2. The gate driving unit circuit according to claim 1 , further comprising a pull-up node control sub-circuit, wherein the pull-up node control sub-circuit is connected to the first pull-up node, the second pull-up node, the pull-down node, and the first voltage terminal, and the pull-up node control sub-circuit is configured to transmit the signal input from the first voltage terminal to the first pull-up node and the second pull-up node under the control of a potential of the pull-down node.

3. The gate driving unit circuit according to claim 2 , wherein:
the pull-up node control sub-circuit comprises a first pull-up node control sub-circuit and a second pull-up node control sub-circuit;
the first pull-up node control sub-circuit is configured to transmit the signal input from the first voltage terminal to the first pull-up node under the control of the potential of the pull-down node; and
the second pull-up node control sub-circuit is configured to transmit the signal input from the first voltage terminal to the second pull-up node under the control of the potential of the pull-down node.

4. The gate driving unit circuit according to claim 3 , wherein:
the first pull-up node control sub-circuit comprises a tenth transistor, and the second pull-up node control sub-circuit comprises a twelfth transistor; and
a gate of the tenth transistor and a gate of the twelfth transistor are commonly connected to the pull-down node, a first electrode of the tenth transistor and a first electrode of the twelfth transistor are commonly connected to the first voltage terminal, a second electrode of the tenth transistor is connected to the first pull-up node, and a second electrode of the twelfth transistor is connected to the second pull-up node.

5. The gate driving unit circuit according to claim 1 , further comprising a pull-down sub-circuit, wherein the pull-down sub-circuit is connected to the pull-down node, the first output terminal, the second output terminal, and the first voltage terminal, and the pull-down sub-circuit is configured to transmit the signal input from the first voltage terminal to the first output terminal and the second output terminal under the control of the pull-down node.

6. The gate driving unit circuit according to claim 5 , wherein:
the pull-down sub-circuit comprises a first pull-down sub-circuit and a second pull-down sub-circuit;
the first pull-down sub-circuit is configured to transmit the signal input from the first voltage terminal to the second output terminal under the control of the potential of the pull-down node; and
the second pull-down sub-circuit is configured to transmit the signal input from the first voltage terminal to the first output terminal under the control of the potential of the pull-down node.

7. The gate driving unit circuit according to claim 6 , wherein:
the first pull-down sub-circuit comprises an eleventh transistor, and the second pull-down sub-circuit comprises a sixteenth transistor; and
a gate of the eleventh transistor and a gate of the sixteenth transistor are commonly connected to the pull-down node, a first electrode of the eleventh transistor and a first electrode of the sixteenth transistor are commonly connected to the first voltage terminal, a second electrode of the eleventh transistor is connected to the second output terminal, and a second electrode of the sixteenth transistor is connected to the first output terminal.

8. The gate driving unit circuit according to claim 1 , further comprising a reset sub-circuit, wherein the reset sub-circuit is connected to a reset control terminal, the first pull-up node, the second pull-up node, the first output terminal, the second output terminal and the first voltage terminal, and the reset sub-circuit is configured to transmit the signal input from the first voltage terminal to the first pull-up node, the second pull-up node, the first output terminal and the second output terminal under the control of a signal input from the reset control terminal.

9. The gate driving unit circuit according to claim 8 , wherein:
the reset sub-circuit comprises a first reset sub-circuit and a second reset sub-circuit;
the first reset sub-circuit is configured to transmit the signal input from the first voltage terminal to the first pull-up node and the second output terminal under the control of the signal input from the reset control terminal; and
the second reset sub-circuit is configured to transmit the signal input from the first voltage terminal to the second pull-up node and the first output terminal under the control of the signal input from the reset control terminal.

10. The gate driving unit circuit according to claim 9 , wherein:
the first reset sub-circuit comprises a second transistor and a fourth transistor, and the second reset sub-circuit comprises a thirteenth transistor and a seventeenth transistor;
a gate of the second transistor, a gate of the fourth transistor, a gate of the thirteenth transistor, and a gate of the seventeenth transistor are commonly connected to the reset control terminal;
a first electrode of the second transistor, a first electrode of the fourth transistor, a first electrode of the thirteenth transistor and a first electrode of the seventeenth transistor are commonly connected to the first voltage terminal; and
a second electrode of the second transistor is connected to the first pull-up node, a second electrode of the fourth transistor is connected to the second output terminal, a sec

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Tech Group Co Ltd

Inventors

• Xiong Xiong
• Zou Yifeng
• Liu Yudong
• Li Youlu

Classifications

• G09G2330/023

  using energy recovery or conservation · CPC title

• G09G3/3674

  Details of drivers for scan electrodes · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title