Semiconductor device

Patent metadata

Field	Value
Publication number	US-9424950-B2
Application number	US-201414315601-A
Country	US
Kind code	B2
Filing date	Jun 26, 2014
Priority date	Jul 10, 2013
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings.

First claim

What is claimed is:

1. A semiconductor device comprising:
a circuit to which an input signal is supplied;
a first transistor;
a second transistor;
a first wiring to which a first potential is supplied, the first wiring electrically connected to a gate of the first transistor and a gate of the second transistor through the circuit;
a second wiring to which a second potential is supplied, the second wiring electrically connected to one of a source and a drain of the first transistor;
a third wiring to which a third potential is supplied, the third wiring electrically connected to the gate of the first transistor and the gate of the second transistor through the circuit; and
a fourth wiring to which a first clock signal is supplied, the fourth wiring electrically connected to one of a source and a drain of the second transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the second transistor,
wherein the circuit is configured to control electrical connections between the gates of the first and second transistors and the first and third wirings in accordance with the input signal and a second clock signal supplied to the circuit,
wherein the first clock signal alternates the second potential and a fourth potential, and the second clock signal alternates the first potential and the third potential,
wherein the second potential is higher than the first potential,
wherein the third potential is higher than the second potential,
wherein the fourth potential is higher than the third potential, and
wherein the first transistor and the second transistor have the same conductivity type.

2. A semiconductor device according to claim 1 , comprising:
a fifth wiring to which the second clock signal is supplied,
wherein the fifth wiring is electrically connected to the circuit.

3. A semiconductor device according to claim 1 , wherein the first transistor and the second transistor each comprise a channel formation region in an oxide semiconductor film.

4. A semiconductor device according to claim 3 , wherein the oxide semiconductor film comprises In, Ga, and Zn.

5. A semiconductor device according to claim 1 ,
wherein the circuit comprises transistors, and
wherein the transistors each include a channel formation region in an oxide semiconductor film.

6. A semiconductor device according to claim 5 ,
wherein a channel width of the first transistor is larger than a channel width of each of the transistors of the circuit.

7. A semiconductor device according to claim 1 , comprising:
a pixel portion; and
a driver circuit comprising the circuit, the first transistor, and the second transistor.

8. A semiconductor device comprising:
a first transistor;
a second transistor; and
a circuit electrically connected to a gate of the first transistor and a gate of the second transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein a first potential and a third potential are supplied to the circuit through a first wiring and a second wiring, respectively,
wherein a second potential is supplied to the other of the source and the drain of the first transistor,
wherein a first clock signal is supplied to the other of the source and the drain of the second transistor, and a second clock signal is supplied to the circuit,
wherein the circuit is configured to control electrical connections between the gates of the first and second transistors and the first and second wirings,
wherein the first clock signal alternates the second potential and a fourth potential, and the second clock signal alternates the first potential and the third potential,
wherein the fourth potential is higher than the third potential,
wherein the third potential is higher than the second potential, and
wherein the second potential is higher than the first potential.

9. A semiconductor device according to claim 8 , wherein the first transistor and the second transistor have the same conductivity type.

10. A semiconductor device according to claim 8 , wherein the first transistor and the second transistor each comprise a channel formation region in an oxide semiconductor film.

11. A semiconductor device according to claim 10 , wherein the oxide semiconductor film comprises In, Ga, and Zn.

12. A semiconductor device according to claim 8 ,
wherein the circuit comprises transistors, and
wherein the transistors each include a channel formation region in an oxide semiconductor film.

13. A semiconductor device according to claim 12 ,
wherein a channel width of the first transistor is larger than a channel width of each of the transistors of the circuit.

14. A semiconductor device according to claim 8 , comprising:
a pixel portion; and
a driver circuit comprising the circuit, the first transistor, and the second transistor.

15. A semiconductor device comprising:
a shift register comprising a first circuit and a second circuit electrically connected to each other, the first circuit and the second circuit each comprising:
a circuit to which an input signal is supplied;
a first transistor, a gate of the first transistor electrically connected to the circuit;
a second transistor, a gate of the second transistor electrically connected to the circuit;
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein a first potential is supplied to the circuit through a first wiring,
wherein a second potential is supplied to the other of the source and the drain of the first transistor through a second wiring, and the second potential is higher than the first potential,
wherein a third potential is supplied to the circuit through a third wiring, and the third potential is higher than the second potential,
wherein the circuit is configured to control electrical connections between the gates of the first and second transistors and the first and third wirings,

wherein a first clock signal is supplied to the other of the source and the drain of the second transistor of the first circuit,
wherein a second clock signal is supplied to the circuit of the first circuit,
wherein a third clock signal is supplied to the other of the source and the drain of the second transistor of the second circuit,
wherein a fourth clock signal is supplied to the circuit of the second circuit,
wherein the first clock signal and the third clock signal each alternate the second potential and a fourth potential, and the second clock signal and the fourth clock signal each alternate the first potential and the third potential,
wherein the fourth potential is higher than the third potential, and
wherein an output signal of the first circuit is supplied to the circuit of the second circuit as the input signal.

16. A semiconductor device according to claim 15 , wherein the first transistor and the second transistor have the same conductivity type.

17. A semiconductor device according to claim 15 , wherein the first transistor and the second transistor each comprise a channel formation region in an oxide semiconductor film.

18. A semiconductor device according to claim 17 , wherein the oxide semiconductor film comprises In, Ga, and Zn.

19. A semiconductor device according to claim 15 ,
wherein the circuit comprises transistors, and
wherein the transistors each include a channel for

Assignees

• Semiconductor Energy Lab

Inventors

• Toyotaka Kouhei
• Koyama Jun
• Miyake Hiroyuki

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3648 Primary

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G3/3275

  Details of drivers for data electrodes · CPC title

• G09G3/3688

  suitable for active matrices only · CPC title