Semiconductor device

Patent metadata

Field	Value
Publication number	US-10256255-B2
Application number	US-201615239006-A
Country	US
Kind code	B2
Filing date	Aug 17, 2016
Priority date	Jul 10, 2013
Publication date	Apr 9, 2019
Grant date	Apr 9, 2019

Abstract

A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings.

First claim

What is claimed is:

1. A semiconductor device comprising:
a pixel portion;
a first sequential circuit;
a second sequential circuit; and
a bus line configured to supply an output signal of the first sequential circuit to the pixel portion,
wherein the first sequential circuit comprises:
a first output terminal electrically connected to the second sequential circuit;
a second output terminal electrically connected to the bus line;
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor;
a first wiring supplied with a first potential;
a second wiring supplied with a second potential; and
a third wiring supplied with a third potential,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein a gate of the third transistor is electrically connected to a gate of the first transistor,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the second transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the one of the source and the drain of the third transistor and the one of the source and the drain of the fourth transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the third wiring,
wherein a gate of the fifth transistor is electrically connected to the third wiring,
wherein the second potential is higher than the first potential,
wherein the third potential is higher than the second potential,
wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor is an n-channel transistor,
wherein one of a source and a drain of the second transistor is electrically connected to the bus line, and the other of the source and the drain is configured to be supplied with a first clock signal,
wherein one of a source and a drain of the sixth transistor is electrically connected to the first output terminal, and the other of the source and the drain of the sixth transistor is configured to be supplied with a second clock signal,
wherein the second transistor and the sixth transistor are n-channel transistors,
wherein the low-level potential of the first clock signal is higher than the low-level potential of the second clock signal, and
wherein the high-level potential of the first clock signal is higher than the high-level potential of the second clock signal.

2. A display device comprising:
a pixel portion;
a first sequential circuit;
a second sequential circuit; and
a bus line configured to supply an output signal of the first sequential circuit to the pixel portion,
wherein the first sequential circuit comprises a first output terminal electrically connected to the second sequential circuit, a second output terminal electrically connected to the bus line, a first transistor and a second transistor,
wherein one of a source and a drain of the first transistor is electrically connected to the bus line, and the other of the source and the drain is configured to be supplied with a first clock signal;
wherein one of a source and a drain of the second transistor is electrically connected to the first output terminal, and the other of the source and the drain of the second transistor is configured to be supplied with a second clock signal,
wherein the first transistor and the second transistor are n-channel transistors,
wherein the low-level potential of the first clock signal is higher than the low-level potential of the second clock signal, and
wherein the high-level potential of the first clock signal is higher than the high-level potential of the second clock signal.

3. A display device according to claim 2 wherein the display device is a liquid crystal device.

4. A display device according to claim 2 wherein the display device is a light emitting device.

5. A display device according to claim 2 wherein the first transistor is normally on.

6. A display device according to claim 2 wherein a channel region of the first transistor and the second transistor comprises an oxide semiconductor.

7. A display device according to claim 6 wherein the oxide semiconductor comprises In, Ga, and Zn.

Assignees

• Semiconductor Energy Lab

Inventors

• Toyotaka Kouhei
• Koyama Jun
• Miyake Hiroyuki

Classifications

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/3688

  suitable for active matrices only · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G3/3275

  Details of drivers for data electrodes · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title