Shift register and display device
US-2015116194-A1 · Apr 30, 2015 · US
US2016365359A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016365359-A1 |
| Application number | US-201615239006-A |
| Country | US |
| Kind code | A1 |
| Filing date | Aug 17, 2016 |
| Priority date | Jul 10, 2013 |
| Publication date | Dec 15, 2016 |
| Grant date | — |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings.
Opening claim text (preview).
What is claimed is: 1 . A semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a first wiring supplied with a first potential; a second wiring supplied with a second potential; and a third wiring supplied with a third potential, wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, wherein a gate of the third transistor is electrically connected to a gate of the first transistor, wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the second transistor, wherein the other of the source and the drain of the fifth transistor is electrically connected to the one of the source and the drain of the third transistor and the one of the source and the drain of the fourth transistor, wherein the other of the source and the drain of the third transistor is electrically connected to the first wiring, wherein the other of the source and the drain of the first transistor is electrically connected to the second wiring, wherein the other of the source and the drain of the fourth transistor is electrically connected to the third wiring, wherein a gate of the fifth transistor is electrically connected to the third wiring, wherein the second potential is higher than the first potential, wherein the third potential is higher than the second potential, and wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor is an n-channel transistor. 2 . The semiconductor device according to claim 1 , further comprising a sixth transistor and a seventh transistor, wherein one of a source and a drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor, wherein the other of the source and the drain of the sixth transistor is electrically connected to the first wiring, wherein a gate of the sixth transistor is electrically connected to the gate of the first transistor, and the gate of the third transistor, and wherein a gate of the seventh transistor is electrically connected to the one of the source and the drain of the third transistor, the one of the source and the drain of the fourth transistor, and the other of the source and the drain of the fifth transistor. 3 . The semiconductor device according to claim 2 , further comprising an eighth transistor, wherein one of a source and a drain of the eighth transistor is electrically connected to the gate of the first transistor, the gate of the third transistor, and the gate of the sixth transistor, wherein a gate of the eighth transistor is electrically connected to a gate of the fourth transistor, and wherein the other of the source and the drain of the eighth transistor is electrically connected to the first wiring. 4 . The semiconductor device according to claim 3 , further comprising a ninth transistor, wherein one of a source and a drain of the ninth transistor is electrically connected to the gate of the first transistor, the gate of the third transistor, the gate of the sixth transistor, and the one of the source and the drain of the eighth transistor, and wherein the other of the source and the drain of the ninth transistor is electrically connected to the third wiring. 5 . The semiconductor device according to claim 4 , further comprising a tenth transistor, wherein one of a source and a drain of the tenth transistor is electrically connected to the gate of the first transistor, the gate of the third transistor, the gate of the sixth transistor, the one of the source and the drain of the eighth transistor, and the other of the source and the drain of the ninth transistor, and wherein the other of the source and the drain of the tenth transistor is electrically connected to the third wiring. 6 . The semiconductor device according to claim 5 , further comprising a eleventh transistor, wherein one of a source and a drain of the eleventh transistor is electrically connected to the gate of the seventh transistor, wherein the other of the source and the drain of the eleventh transistor is electrically connected to the one of the source and the drain of the third transistor, the one of the source and the drain of the fourth transistor, and the other of the source and the drain of the fifth transistor, and wherein a gate of the eleventh transistor is electrically connected to the third wiring. 7 . The semiconductor device according to claim 5 , further comprising a twelfth transistor, wherein one of a source and a drain of the twelfth transistor is electrically connected to the other of the source and the drain of the fifth transistor and the gate of the seventh transistor, wherein the other of the source and the drain of the twelfth transistor is electrically connected to the one of the source and the drain of the third transistor and the one of the source and the drain of the fourth transistor, and wherein a gate of the twelfth transistor is electrically connected to the third wiring. 8 . A semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a first wiring supplied with a first potential; a second wiring supplied with a second potential; and a third wiring supplied with a third potential, wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, wherein a gate of the third transistor is electrically connected to a gate of the first transistor, wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the second transistor, wherein the other of the source and the drain of the fifth transistor is electrically connected to the one of the source and the drain of the third transistor and the one of the source and the drain of the fourth transistor, wherein the other of the source and the drain of the third transistor is electrically connected to the first wiring, wherein the other of the source and the drain of the first transistor is electrically connected to the second wiring, wherein the other of the source and the drain of the fourth transistor is electrically connected to the third wiring, wherein a gate of the fifth transistor is electrically connected to the third wiring, wherein the second potential is higher than the first potential, wherein the third potential is higher than the second potential, and wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor comprises an oxide semiconductor film comprising a channel formation region. 9 . The semiconductor device according to claim 8 , further comprising a sixth transistor and a seventh transistor, wherein one of a source and a drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor, wherein the other of the source and the drain of the sixth transistor is electrically connected to the first wiring, wherein a gate of the sixth transistor is electrically connected to the gate of the first transistor, and the gate of the third transistor, and wherein a gate of the seventh transistor is electrically connecte
in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title
Wiring, e.g. gate line, drain line · CPC title
Details of timing specific for flat panels, other than clock recovery · CPC title
Organisation of a multiplicity of shift registers · CPC title
suitable for active matrices only · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.