Plugs for interconnect lines for advanced integrated circuit structure fabrication

Patent metadata

Field	Value
Publication number	US-11404559-B2
Application number	US-202017027568-A
Country	US
Kind code	B2
Filing date	Sep 21, 2020
Priority date	Nov 30, 2017
Publication date	Aug 2, 2022
Grant date	Aug 2, 2022

Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.

First claim

What is claimed is:

1. A method of fabricating integrated circuit structure, the method comprising:
forming a line trench in an upper portion of an interlayer dielectric (ILD) material layer formed above an underlying metallization layer;
forming a via trench in a lower portion of the ILD material layer, the via trench exposing a metal line of the underlying metallization layer;
forming a sacrificial material above the ILD material layer and in the line trench and the via trench;
patterning the sacrificial material to form an opening to break a continuity of the sacrificial material in the line trench;
filling the opening in the sacrificial material with a dielectric material to form a dielectric plug having an upper surface above an upper surface of the ILD material;
removing the sacrificial material and leaving the dielectric plug to remain;
filling the line trench and the via trench with a conductive material; and
planarizing the dielectric plug and the conductive material to provide a planarized dielectric plug breaking a continuity of the conductive material in the line trench.

2. The method of claim 1 , wherein filling the opening of the sacrificial material with the dielectric material comprises filling with a metal oxide material.

3. The method of claim 2 , wherein the metal oxide material is aluminum oxide.

4. The method of claim 1 , wherein filling the opening of the sacrificial material with the dielectric material comprises filling using atomic layer deposition (ALD).

5. The method of claim 1 , wherein the forming the sacrificial material comprises forming a hardmask material comprising carbon.

6. A method of fabricating an integrated circuit structure, the method comprising:
forming an inter-layer dielectric (ILD) layer above a substrate;
forming a conductive interconnect structure in a trench in the ILD layer, the conductive interconnect structure having a first conductive line and a second conductive line, an end of the first conductive line laterally spaced apart and electrically isolated from an end of the second conductive line, wherein the first and second conductive lines of the conductive interconnect structure have a bottom on the ILD layer; and
forming a dielectric plug between and in lateral contact with the ends of the first and second conductive lines of the conductive interconnect structure, the dielectric plug comprising a metal oxide material, the dielectric plug having a different composition than the ILD layer, wherein the dielectric plug has a bottom on the ILD layer, the bottom of the dielectric plug substantially co-planar with the bottom of the first and second conductive lines of the conductive interconnect structure.

7. The method of claim 6 , wherein the metal oxide material is aluminum oxide.

8. The method of claim 6 , wherein the dielectric plug has an approximately vertical seam spaced approximately equally from the first conductive line of the conductive interconnect structure and from the second conductive line of the conductive interconnect structure.

9. The method of claim 6 , further comprising:
forming a first conductive via in a second trench in the ILD layer, the first conductive via below the bottom of the first conductive line, and the first conductive via electrically coupled to the first conductive line; and
forming a second conductive via in a third trench in the ILD layer, the second conductive via below the bottom of the second conductive line, and the second conductive via electrically coupled to the second conductive line.

10. The method of claim 6 , wherein the first and second conductive lines of the conductive interconnect structure comprise a conductive barrier liner and a conductive fill material, the conductive fill material comprising cobalt.

11. A method of fabricating an integrated circuit structure, the method comprising:
forming a first plurality of conductive interconnect structures in and spaced apart by a first inter-layer dielectric (ILD) layer above a substrate, wherein individual ones of the first plurality of conductive interconnect structures have a dielectric plug in lateral contact with and electrically isolating corresponding ends of conductive lines, wherein the conductive lines have a bottom on the first ILD layer, the dielectric plug having a bottom on the first ILD layer, the bottom of the dielectric plug substantially co-planar with the bottom of the conductive lines, and the dielectric plug comprising a metal oxide material, the dielectric plug having a composition different than the first ILD layer; and
forming a second plurality of conductive interconnect structures in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect structures have conductive lines having ends separated by the second ILD layer.

12. The method of claim 11 , wherein the metal oxide material is aluminum oxide.

13. The method of claim 12 , wherein the first ILD layer and the second ILD layer comprise a carbon-doped silicon oxide material.

14. The method of claim 11 , wherein the conductive lines of the first plurality of conductive interconnect structures comprise a first conductive barrier liner and a first conductive fill material, the second plurality of conductive interconnect structures comprise a second conductive barrier liner and a second conductive fill material, and wherein the first conductive fill material is different in composition from the second conductive fill material.

15. The method of claim 11 , wherein the first conductive fill material comprises cobalt, and the second conductive fill material comprises copper.

16. The method of claim 11 , wherein the conductive lines of the first plurality of conductive interconnect structures have a first pitch, the conductive lines of the second plurality of conductive interconnect structures have a second pitch, and wherein the second pitch is greater than the first pitch.

17. The method of claim 11 , wherein the conductive lines of the first plurality of conductive interconnect structures have a first width, the conductive lines of the second plurality of conductive interconnect structures have a second width, and wherein the second width is greater than the first width.

18. A method of fabricating a computing device, the method comprising:
providing a board; and
coupling a component to the board, the component including an integrated circuit structure, comprising:
an inter-layer dielectric (ILD) layer above a substrate;
a conductive interconnect structure in a trench in the ILD layer, the conductive interconnect structure having a first conductive line and a second conductive line, an end of the first conductive line laterally spaced apart and electrically isolated from an end of the second conductive line, wherein the first and second conductive lines of the conductive interconnect structure have a bottom on the ILD layer; and
a dielectric plug between and in lateral contact with the ends of the first and second conductive lines of the conductive interconnect structure, the dielectric plug comprising a metal oxide material, the dielectric plug having a different composition than the ILD layer, wherein the dielectric plug has a bottom on the ILD layer, the bottom of the dielectric plug substantially co-planar with the bottom of the first and second conductive lines of the conductive interconnect structure.

19. The method of claim 18 , the method further comprising:
coupling a memory to the board.

20

Assignees

• Intel Corp

Inventors

• Yeoh Andrew W
• Jin Ilsup
• Kandas Angelo
• Hattendorf Michael L
• Auth Christopher P

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W72/30

  Die-attach connectors · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/851

  Dispositions of multiple connectors or interconnections · CPC title