Method of controlling wafer bow in a type III-V semiconductor device

Patent metadata

Field	Value
Publication number	US-11387355-B2
Application number	US-202016895585-A
Country	US
Kind code	B2
Filing date	Jun 8, 2020
Priority date	Jun 21, 2017
Publication date	Jul 12, 2022
Grant date	Jul 12, 2022

Abstract

A type IV semiconductor substrate having a main surface is provided. A type III-V semiconductor channel region that includes a two-dimensional carrier gas is formed over the type IV semiconductor substrate. A type III-V semiconductor lattice transition region that is configured to alleviate mechanical stress arising from lattice mismatch is formed between the type IV semiconductor substrate and the type III-V semiconductor channel region. Forming the type III-V semiconductor lattice transition region includes forming a first lattice transition layer having a first metallic concentration over the type IV semiconductor substrate, forming a third lattice transition layer having a third metallic concentration that is higher than the first metallic concentration over the first lattice transition layer, and forming a fourth lattice transition layer having a fourth metallic concentration that is lower than the first metallic concentration over the third lattice transition layer.

First claim

The invention claimed is:

1. A type III-V semiconductor device, comprising:
a type IV semiconductor substrate comprising a main surface;
a type III-V semiconductor lattice transition region formed over the main surface of the semiconductor substrate; and
a type III-V semiconductor channel region formed over the type III-V semiconductor lattice transition region, the type-III-V semiconductor channel region comprising a two-dimensional carrier gas,
wherein the type III-V semiconductor lattice transition region is electrically inactive and is configured to alleviate lattice mismatch between the type IV semiconductor substrate and the type III-V semiconductor channel region,
wherein the type III-V semiconductor lattice transition region comprises:
a first lattice transition layer formed over the type IV semiconductor substrate, the first lattice transition layer having a first metallic concentration;
a third lattice transition layer formed over the first lattice transition layer, the third lattice transition layer having a third metallic concentration that is higher than the first metallic concentration;
a second lattice transition layer between the first transition layer and the third transition layer, the second lattice transition layer having a second metallic concentration that is lower than the first metallic concentration and is lower than the third metallic concentration; and
a fourth lattice transition layer formed over the third lattice transition layer, the fourth lattice transition layer having a fourth metallic concentration that is lower than the first metallic concentration.

2. The type III-V semiconductor device of claim 1 , wherein the first lattice transition layer exerts a compressive stress on adjacent semiconductor layers, and wherein the third lattice transition layer exerts a tensile stress on adjacent semiconductor layers.

3. The type III-V semiconductor device of claim 2 , wherein the tensile stress exerted by the third lattice transition layer completely counteracts the tensile stress exerted by the first lattice transition layer.

4. The type III-V semiconductor device of claim 2 , wherein a substrate bow measured at an upper surface of the type III-V semiconductor device is less than 1 μm.

5. The type III-V semiconductor device of claim 1 , wherein the type IV semiconductor substrate comprises silicon, wherein the first, second and third lattice transition layers each comprise aluminum gallium nitride, wherein the first, second and third metallic concentrations correspond to an aluminum concentration of the first, second and third lattice transition layers, respectively, and wherein the type III-V semiconductor channel region comprises a gallium nitride buffer layer that is formed directly on the third lattice transition layer.

6. A type III-V semiconductor device, comprising:
a type IV semiconductor substrate comprising a main surface;
a type III-V semiconductor lattice transition region formed over the main surface of the semiconductor substrate; and
a type III-V semiconductor channel region formed over the type III-V semiconductor lattice transition region, the type-III-V semiconductor channel region comprising a two-dimensional carrier gas,
wherein the type III-V semiconductor lattice transition region is electrically inactive and is configured to alleviate lattice mismatch between the type IV semiconductor substrate and the type III-V semiconductor channel region,
wherein the type III-V semiconductor lattice transition region comprises:
a first lattice transition layer formed over the type IV semiconductor substrate, wherein the first lattice transition layer is a layer of GaN or AlGaN;
a third lattice transition layer formed over the first lattice transition layer, wherein the third lattice transition layer is a layer of AlGaN with a higher aluminum content than the first lattice transition layer;
a fourth lattice transition layer formed over the third lattice transition layer, wherein the fourth lattice transition layer is a layer of AlGaN with a lower aluminum content as the first lattice transition layer.

7. The type III-V semiconductor device of claim 6 , wherein the aluminum content of the third lattice transition layer is between 60% and 100%.

8. The type III-V semiconductor device of claim 7 , wherein the aluminum content of the first lattice transition layer is between 60% and 80%, and wherein the aluminum content of the fourth lattice transition layer is between 30% and 50%.

9. The type III-V semiconductor device of claim 6 , further comprising a nucleation layer of AlN and a buffer layer of GaN or AlGaN, wherein the type III-V semiconductor lattice transition region is disposed directly on the nucleation layer, and wherein the buffer layer is disposed directly on the type III-V semiconductor lattice transition region.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Park Seong-Eun
• Wan Jianwei
• Tungare Mihir
• Kim Peter
• Kannan Srinivasan

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10P14/3251

  consisting of three or more layers · CPC title

• H10P14/3216

  Nitrides · CPC title

• H10P14/2921

  being crystalline insulating materials · CPC title

• H10P14/2905 Primary

  Silicon, silicon germanium or germanium · CPC title