Semiconductor heterostructure with stress management

Patent metadata

Field	Value
Publication number	US-9537054-B2
Application number	US-201514686845-A
Country	US
Kind code	B2
Filing date	Apr 15, 2015
Priority date	Apr 15, 2014
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.

First claim

What is claimed is:

1. A heterostructure comprising:
a substrate; and
a group III nitride layer epitaxially grown on the substrate, wherein the group III nitride layer includes:
a plurality of sub-layers of a first group III nitride material and having a first thickness; and
a plurality of thin sub-layers of a second group III nitride material and having a second thickness, wherein the plurality of sub-layers alternate with the plurality of thin sub-layers, wherein the first group III nitride material includes a molar fraction of gallium of at least 0.05, wherein a molar fraction of gallium in the first group III nitride material differs from the molar fraction of gallium in the second group III nitride material by at least 0.05, and wherein the second thickness is at most five percent of the first thickness.

2. The heterostructure of claim 1 , further comprising a buffer layer epitaxially grown directly on the substrate, wherein the group III nitride layer is grown over the buffer layer, and wherein the group III nitride layer is one of: an n-type contact layer or an n-type cladding layer, for an optoelectronic device fabricated using the heterostructure.

3. The heterostructure of claim 2 , wherein the optoelectronic device is configured to operate as a light emitting diode.

4. The heterostructure of claim 1 , wherein the second thickness is between approximately 0.2 nanometers and approximately 2 nanometers.

5. The heterostructure of claim 1 , wherein the second thickness is at most two percent of the first thickness.

6. The heterostructure of claim 1 , wherein the first thickness is between approximately 20 nanometers and approximately 500 nanometers.

7. The heterostructure of claim 1 , wherein the second group III nitride material is aluminum nitride.

8. The heterostructure of claim 1 , wherein the first group III nitride material is Al x Ga 1-x N with 0.4<x<0.7.

9. The heterostructure of claim 1 , wherein the group III nitride layer includes at least twenty thin sub-layers.

10. An optoelectronic device comprising:
a substrate; and
an n-type layer formed of group III nitride materials located on the substrate, wherein the n-type layer includes:
a plurality of sub-layers of a first group III nitride material and having a first thickness; and
a plurality of thin sub-layers of a second group III nitride material and having a second thickness, wherein the plurality of sub-layers alternate with the plurality of thin sub-layers, wherein the first group III nitride material includes a molar fraction of gallium of at least 0.05, wherein a molar fraction of gallium in the first group III nitride material differs from the molar fraction of gallium in the second group III nitride material by at least 0.05, and wherein the second thickness is at most five percent of the first thickness.

11. The device of claim 10 , wherein the device is configured to operate as a light emitting diode, the device further including an active region adjacent to the n-type layer, wherein the n-type layer is one of: an n-type contact layer or an n-type cladding layer.

12. The device of claim 11 , wherein the plurality of sub-layers have a molar fraction of aluminum within approximately twenty percent of a molar fraction of aluminum of a first barrier in the active region adjacent to the n-type layer.

13. The device of claim 10 , wherein the device is configured to operate as a high electron mobility transistor, wherein the n-type layer is a carrier electronic layer.

14. The device of claim 10 , wherein the second thickness is less than a tunneling length of carriers in the n-type layer.

15. The device of claim 10 , wherein the first group III nitride material is AlGaN with a molar fraction of aluminum between 0.4 and 0.7, wherein the second group III nitride material is AlN, wherein the first thickness is in a range of 20 nanometers to 500 nanometers, and wherein the second thickness is in a range of 0.2 nanometers to 2 nanometers.

16. The device of claim 15 , wherein at least one of: the molar fraction of aluminum, the first thickness, or the second thickness, increases or decreases along the lateral height of the n-type layer.

17. A method of fabricating a device, the method comprising:
forming a group III nitride layer on a substrate, wherein the group III nitride layer includes:
a plurality of sub-layers of a first group III nitride material and having a first thickness; and
a plurality of thin sub-layers of a second group III nitride material and having a second thickness, wherein the plurality of sub-layers alternate with the plurality of thin sub-layers, wherein the first group III nitride material includes a molar fraction of gallium of at least 0.05, wherein a molar fraction of gallium in the second group III nitride material differs from the molar fraction of gallium in the first group III nitride material by at least 0.05, and wherein the second thickness is at most five percent of the first thickness.

18. The method of claim 17 , wherein the first group III nitride material is AlGaN with a molar fraction of aluminum between 0.4 and 0.7, wherein the second group III nitride material is AlN, wherein the first thickness is in a range of 20 nanometers to 500 nanometers, and wherein the second thickness is in a range of 0.2 nanometers to 2 nanometers.

19. The method of claim 17 , further comprising selecting the second thickness based on a sheet resistivity of the n-type layer prior to the forming.

20. The method of claim 17 , further comprising selecting the first thickness and a total number of the plurality of thin sub-layers based on a target amount of wafer bowing.

Assignees

• Sensor Electronic Tech Inc

Inventors

• Billingsley Daniel D
• Kennedy Robert M
• Sun Wenhong
• Jain Rakesh
• Shatalov Maxim S
• Dobrinsky Alexander
• Shur Michael
• Gaska Remigijus

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10P14/3252

  Alternating layers, e.g. superlattice · CPC title

• H10P14/3216

  Nitrides · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H01L33/0075

  Electricity · mapped topic