Heterostructure including a composite semiconductor layer

Patent metadata

Field	Value
Publication number	US-9818826-B2
Application number	US-201414519230-A
Country	US
Kind code	B2
Filing date	Oct 21, 2014
Priority date	Oct 21, 2013
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A heterostructure for use in an electronic or optoelectronic device is provided. The heterostructure includes one or more composite semiconductor layers. The composite semiconductor layer can include sub-layers of varying morphology, at least one of which can be formed by a group of columnar structures (e.g., nanowires). Another sub-layer in the composite semiconductor layer can be porous, continuous, or partially continuous.

First claim

What is claimed is:

1. A heterostructure comprising:
a composite semiconductor layer including a plurality of sub-layers, wherein the plurality of sub-layers includes:
a first sub-layer comprising a plurality of nanowires with a characteristic spacing between each of the nanowires that ranges from 2 nm to 100 nm,
a second sub-layer immediately adjacent to the first sub-layer, wherein the second sub-layer includes a partially continuous interior portion with isolated cavities formed therein, the isolated cavities having an arrangement distinct from the spacing between the plurality of nanowires, and wherein the plurality of nanowires of the first sub-layer contact the second sub-layer without penetrating into any of the isolated cavities.

2. The heterostructure of claim 1 , wherein the composite semiconductor layer is formed of aluminum nitride.

3. The heterostructure of claim 1 , wherein each of the plurality of nanowires has a characteristic diameter in a range of 5-500 nm, and a characteristic length in a range of 50 nm-5 microns.

4. The heterostructure of claim 1 , the composite semiconductor layer further comprising a third sub-layer immediately adjacent to the second sub-layer, wherein third sub-layer is essentially continuous.

5. The heterostructure of claim 4 , wherein the third sub-layer is a superlattice including a plurality of alternating tensile and compressive layers.

6. The heterostructure of claim 1 , further comprising a substrate, wherein the composite semiconductor layer is immediately adjacent to the substrate.

7. The heterostructure of claim 6 , wherein a top surface of the composite semiconductor layer has a curvature at least five percent less than a top surface of the substrate on which the composite semiconductor layer is located.

8. The heterostructure of claim 1 , wherein a characteristic height-to-diameter ratio of each of the plurality of nanowires is at least one.

9. The heterostructure of claim 1 , wherein the composite semiconductor layer further includes:
a third sub-layer comprising a plurality of nanowires; and
a fourth sub-layer immediately adjacent to the third sub-layer, wherein the fourth sub-layer is at least partially continuous.

10. The heterostructure of claim 9 , wherein the plurality of nanowires of the third sub-layer have at least one characteristic dimension that differs from a corresponding at least one characteristic dimension of the plurality of nanowires of the first sub-layer by at least one percent.

11. The heterostructure of claim 1 , wherein each of the plurality of nanowires has at least one of: a variable composition or a variable doping.

12. The heterostructure of claim 1 , wherein the composite semiconductor layer further includes a template layer, wherein the template layer defines locations of the plurality of nanowires.

13. The heterostructure of claim 12 , wherein the template layer includes a plurality of openings, and wherein the plurality of nanowires are located in the plurality of openings.

14. An optoelectronic device comprising:
a sapphire substrate; and
a buffer layer immediately adjacent to the sapphire substrate, wherein the buffer layer is formed of aluminum nitride and includes a plurality of sub-layers formed therein, wherein the plurality of sub-layers includes:
a first sub-layer comprising a plurality of nanowires with a characteristic spacing between each of the nanowires that ranges from 2 nm to 100 nm; and
a second sub-layer immediately adjacent to the first sub-layer, wherein the second sub-layer includes a partially continuous interior portion with isolated cavities formed therein, the isolated cavities having an arrangement distinct from the spacing between the plurality of nanowires, and wherein the plurality of nanowires of the first sub-layer contact the second sub-layer without penetrating into any of the isolated cavities.

15. The device of claim 14 , wherein each of the plurality of nanowires has a characteristic diameter in a range of 5-500 nm, and a characteristic length in a range of 50 nm-5 microns.

16. The device of claim 14 , further comprising a group III nitride n-type layer immediately adjacent to the buffer layer.

17. The device of claim 14 , the composite semiconductor layer further comprising a third sub-layer immediately adjacent to the second sub-layer, wherein third sub-layer is essentially continuous.

18. A method comprising:
growing a composite semiconductor layer including a plurality of sub-layers, wherein the plurality of sub-layers includes:
a first sub-layer comprising a plurality of nanowires with a characteristic spacing between each of the nanowires that ranges from 2 nm to 100 nm; and
a second sub-layer immediately adjacent to the first sub-layer, wherein the second sub-layer layer includes a partially continuous interior portion with isolated cavities formed therein, the isolated cavities having an arrangement distinct from the spacing between the plurality of nanowires, and wherein the plurality of nanowires of the first sub-layer contact the second sub-layer without penetrating into any of the isolated cavities.

19. The method of claim 18 , wherein the growing includes growing the first sub-layer using a plurality of growth steps including:
epitaxially growing AlN nucleation islands having a target characteristic diameter and a target characteristic spacing using a set of growth conditions promoting Al-species diffusion at the growth surface; and
epitaxially growing the plurality of nanowires over the nucleation islands.

20. The method of claim 19 , wherein the epitaxially growing AlN nucleation islands includes selecting at least one of: a V/III ratio or a growth temperature based on the target characteristic diameter.

Assignees

• Sensor Electronic Tech Inc

Inventors

• Shatalov Maxim S
• Jain Rakesh
• Yang Jinwei
• Dobrinsky Alexander
• Shur Michael
• Gaska Remigijus

Classifications

• H10P14/3451

  Structure · CPC title

• H10P14/3416

  Nitrides · CPC title

• H10P14/3256

  Microstructure · CPC title

• H10P14/3251

  consisting of three or more layers · CPC title

• H10P14/3216

  Nitrides · CPC title