Gallium nitride epitaxial structures for power devices

Patent metadata

Field	Value
Publication number	US-10355120-B2
Application number	US-201815864977-A
Country	US
Kind code	B2
Filing date	Jan 8, 2018
Priority date	Jan 18, 2017
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

A method for making a multilayered device on an engineered substrate having a substrate coefficient of thermal expansion includes growing a buffer layer on the engineered substrate, and growing a first epitaxial layer on the buffer layer. The first epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.

First claim

What is claimed is:

1. A method for making a multilayered device on an engineered substrate having a substrate coefficient of thermal expansion, the method comprising:
providing an engineered substrate, the engineered substrate comprising:
a polycrystalline substrate;
a barrier layer encapsulating the polycrystalline substrate;
a bonding layer coupled to the barrier layer; and
a single crystalline silicon layer coupled to the bonding layer;

growing a buffer layer on the single crystalline silicon layer; and
growing a first epitaxial layer on the buffer layer, wherein the first epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.

2. The method of claim 1 wherein the first epitaxial layer comprises doped gallium nitride (GaN).

3. The method of claim 1 wherein the first epitaxial layer comprises aluminum gallium nitride (AlGaN).

4. The method of claim 2 further comprising:
growing a second epitaxial layer comprising undoped GaN coupled to the first epitaxial layer; and
growing a third epitaxial layer coupled to the second epitaxial layer;
wherein an interface between the second epitaxial layer and the third epitaxial layer forms a conducting channel of a high-electron-mobility transistor (HEMT).

5. The method of claim 4 wherein the third epitaxial layer comprises aluminum gallium nitride (AlGaN) or indium aluminum nitride (InAlN).

6. The method of claim 1 wherein the the single crystalline silicon layer is formed on the bonding layer by a layer transfer process.

7. The method of claim 1 wherein the single crystalline silicon layer is transferred to the bonding layer by exfoliation.

8. The method of claim 1 further comprising forming an electrical contact electrically coupled to the single crystalline silicon layer through the engineered substrate.

9. The method of claim 1 further comprising:
growing a conducting epitaxial layer disposed between the buffer layer and the first epitaxial layer; and
forming an electrical contact electrically coupled to the conducting epitaxial layer through the first epitaxial layer.

10. The method of claim 9 further comprising forming a partial monolayer of silicon nitride disposed between the buffer layer and the conducting epitaxial layer.

11. A method for making a multilayered high electron mobility transistor (HEMT) device on an engineered substrate having a substrate coefficient of thermal expansion, the method comprising:
growing a buffer layer on the engineered substrate;
growing a first epitaxial layer coupled to the buffer layer, wherein the first epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion;
growing an aluminum gallium nitride (AlGaN) back barrier layer coupled to the first epitaxial layer;
growing an undoped gallium nitride (GaN) layer coupled to the AlGaN back barrier layer; and
growing a barrier layer coupled to the undoped GaN layer.

12. The method of claim 11 wherein the first epitaxial layer comprises unintentionally doped GaN.

13. The method of claim 11 wherein the first epitaxial layer comprises alternating layers of undoped GaN and doped GaN.

14. The method of claim 13 wherein the doped GaN comprises carbon-doped GaN (C-GaN) or iron-doped GaN (Fe-GaN).

15. The method of claim 11 wherein the AlGaN back barrier layer has an aluminum mole fraction ranging from about 3% to about 15%.

16. The method of claim 11 wherein the engineered substrate comprises a single-crystal film bonded to a structure including a polycrystalline ceramic core.

17. An epitaxial semiconductor structure comprising:
an engineered substrate having a substrate coefficient of thermal expansion, the engineered substrate comprising:
a polycrystalline ceramic core;
a barrier layer encapsulating the polycrystalline ceramic core;
a bonding layer coupled to the barrier layer; and
a single crystalline silicon layer coupled to the bonding layer;

a buffer layer coupled to the single crystalline silicon layer; and
a first epitaxial layer formed on the buffer layer, wherein the first epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.

18. The epitaxial semiconductor structure of claim 17 wherein the first epitaxial layer comprises doped gallium nitride (GaN).

19. The epitaxial semiconductor structure of claim 17 wherein the first epitaxial layer comprises aluminum gallium nitride (AlGaN).

20. The epitaxial semiconductor structure of claim 17 further comprising:
a second epitaxial layer comprising undoped GaN coupled to the first epitaxial layer; and
a third epitaxial layer coupled to the second epitaxial layer;
wherein an interface between the second epitaxial layer and the third epitaxial layer forms a conducting channel of a high-electron-mobility transistor (HEMT).

21. The epitaxial semiconductor structure of claim 20 wherein the third epitaxial layer comprises aluminum gallium nitride (AlGaN) or indium aluminum nitride (InAlN).

22. The epitaxial semiconductor structure of claim 17 wherein the the single crystalline silicon layer is transferred to the bonding layer by exfoliation.

23. The epitaxial semiconductor structure of claim 17 wherein the single crystalline silicon layer is formed on the bonding layer by a layer transfer process.

Assignees

• Qromis Inc

Inventors

• Odnoblyudov Vladimir
• Lester Steve
• Aktas Ozgur

Classifications

• H10P90/00 Primary

  Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/3416

  Nitrides · CPC title

• H10P14/3251

  consisting of three or more layers · CPC title

• H10P14/3246

  Monolayers · CPC title