Control flow barrier and reconfigurable data processor

Patent metadata

Field	Value
Publication number	US-11386038-B2
Application number	US-201916407675-A
Country	US
Kind code	B2
Filing date	May 9, 2019
Priority date	May 9, 2019
Publication date	Jul 12, 2022
Grant date	Jul 12, 2022

Abstract

A reconfigurable data processor comprises an array of processing units arranged to perform execution fragments of a data processing operation. A control barrier network is coupled to processing units in the array. The control barrier network comprises a control bus configurable to form signal routes in the control barrier network, and a plurality of control barrier logic units having inputs and outputs connected to the control bus and to the array of processing units. The logic units in the plurality of logic units are configurable to consume source tokens and status signals on the inputs and produce barrier tokens on the outputs based on the source tokens and status signals on the inputs. Also, the logic units can produce enable signals for the array of processing units based on the source tokens and status signals on the inputs.

First claim

What is claimed is:

1. A processing system, comprising:
an array of processing units arranged to perform execution fragments of a data processing operation, a processing unit in the array arranged to respond to an enable signal to enable execution of an execution fragment by the processing unit, and to generate a status signal usable to indicate status of the execution fragments performed by the processing unit; and
a control barrier network coupled to processing units in the array including switches set by configuration data before execution of the execution fragments, the control barrier network comprising:
a control bus configurable by the configuration data to form signal routes in the control barrier network; and
a plurality of logic units having inputs and outputs connected to the control bus and to the array of processing units, a logic unit in the plurality of logic units operatively coupled to the processing unit in the array of processing units and configurable by the configuration data to consume source tokens and the status signal from the processing unit on the inputs and to produce barrier tokens and the enable signal on the outputs based on the source tokens and the status signal on the inputs.

2. The processing system of claim 1 , wherein the control bus comprises a configurable interconnect configurable by configuration data to connect lines on the control bus carrying barrier tokens, produced on the outputs of logic units as source tokens, to inputs of logic units that consume the source tokens.

3. The processing system of claim 1 , wherein processing units in the array comprise configurable logic units, configurable by configuration data to execute execution fragments.

4. The processing system of claim 1 , wherein the control bus is configurable to form signal routes connecting the output of one logic unit in the plurality of logic units as a source token to inputs of more than one logic unit in the plurality of logic units.

5. The processing system of claim 1 , wherein the control bus is configurable to form signal routes providing source tokens sourced from more than one logic unit in the plurality of logic units to inputs of one logic unit in the plurality of logic units.

6. The processing system of claim 1 , the logic unit including:
a token store having inputs and outputs;
a configurable input circuit configurable to connect selected lines in the control bus and a status signal line of the processing unit to inputs of the token store; and
a token output circuit configurable to provide a barrier token to the control bus in response to a first configurable combination of the outputs of the token store.

7. The processing system of claim 1 , the logic unit including:
a token store having inputs and outputs;
a configurable input circuit configurable to connect selected lines in the control bus and a status signal line of the processing unit to inputs of the token store;
a token output circuit configurable to provide a barrier token to the control bus in response to a first configurable combination of the outputs of the token store;
a feedback circuit configurable to provide a feedback signal in response to a second configurable combination of the outputs of the token store, to clear the token store; and
an enable circuit to provide the enable signal to the processing unit in response to outputs of the token store.

8. The processing system of claim 1 , including a data bus interconnecting the array of processing units, and separate from the control bus.

9. The processing system of claim 8 , wherein the data bus comprises a packet-switched network.

10. A configurable processor, comprising:
an array of configurable units, including a configuration store to store configuration data to configure the array of configurable units to perform execution fragments of a data processing operation, wherein the array of configurable units is configured before execution of the execution fragments;
a bus system interconnecting the configurable units in the array of configurable units;
a plurality of control barrier logic units, control barrier logic units in the plurality of control barrier logic units being operatively coupled to one or more configurable units in the array of configurable units and to the bus system, each control barrier logic unit in the plurality of control barrier logic units including
a token store having inputs and outputs;
a configurable input circuit configurable by the configuration data to connect selected lines in the bus system to inputs of the token store; and
a configurable output circuit configurable by the configuration data to provide a barrier token to the bus system in response to a first combination set by the configuration data of the outputs of the token store.

11. The configurable processor of claim 10 , wherein a configurable unit in the array includes an enable input, and the control barrier logic unit includes:
circuits to apply an enable signal to the enable input of the configurable unit in response to a second combination set by the configuration data of the outputs of the token store.

12. The configurable processor of claim 11 , wherein a configurable unit in the array generates status signals on status lines, and the configurable input circuit is configurable by the configuration data to connect one or more of the status lines as an input or inputs to the token store.

13. The configurable processor of claim 10 , wherein a configurable unit in the array generates status signals on status lines, and the configurable input circuit is configurable by the configuration data to connect one or more of the status lines as an input or inputs to the token store.

14. The configurable processor of claim 10 , the control barrier logic unit including
a feedback circuit configurable by the configuration data to provide a feedback signal in response to outputs of the token store, to clear the token store.

15. The configurable processor of claim 10 , the control barrier logic unit including
a feedback circuit configurable by the configuration data to provide the barrier token to clear the token store.

16. The configurable processor of claim 14 , wherein a configurable unit in the array comprises processing elements configurable by the configuration data to perform execution fragments of a data processing operation, an execution fragment being enabled by an enable signal and generating status signals, and the configurable input circuit is configurable by the configuration data to apply a status signal from the execution fragment as an input to the token store; and
the control barrier logic unit includes circuits to apply the enable signal for the execution fragment in response to source tokens in the token store.

17. The configurable processor of claim 16 , wherein the enable signal is applied in response to a second combination set by the configuration data of the outputs of the token store.

18. The configurable processor of claim 10 , wherein the bus system includes a data bus and a control bus, and the configurable input circuits are connected to lines in the control bus.

19. The configurable processor of claim 18 , wherein the control bus comprises a configurable interconnect, settable by the configuration data to connect lines on the control bus coupled to the configurable input circuit to sources of source tokens.

20. A configurable processor, comprising:
an array of configurable units including a configuration store to store configuration data to configur

Assignees

• Sambanova Systems Inc

Inventors

• Prabhakar Raghu
• Shah Manish K
• Sivaramakrishnan Ram
• Nataraja Pramod
• Jackson David Brian
• Grohoski Gregory Frederick

Classifications

• G06F15/17325

  Synchronisation; Hardware support therefor (intertask synchronisation G06F9/52) · CPC title

• G06F9/522

  Barrier synchronisation · CPC title

• G06F15/80

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title

• G06F15/8007 Primary

  single instruction multiple data [SIMD] multiprocessors · CPC title

• G06F13/20

  for access to input/output bus · CPC title