Checkpointed buffer for re-entry from runahead

Patent metadata

Field	Value
Publication number	US-9875105-B2
Application number	US-201213463627-A
Country	US
Kind code	B2
Filing date	May 3, 2012
Priority date	May 3, 2012
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

Embodiments related to re-dispatching an instruction selected for re-execution from a buffer upon a microprocessor re-entering a particular execution location after runahead are provided. In one example, a microprocessor is provided. The example microprocessor includes fetch logic, one or more execution mechanisms for executing a retrieved instruction provided by the fetch logic, and scheduler logic for scheduling the retrieved instruction for execution. The example scheduler logic includes a buffer for storing the retrieved instruction and one or more additional instructions, the scheduler logic being configured, upon the microprocessor re-entering at a particular execution location after runahead, to re-dispatch, from the buffer, an instruction that has been previously dispatched to one of the execution mechanisms.

First claim

The invention claimed is:

1. A microprocessor, comprising:
fetch logic;
one or more execution mechanisms for executing a retrieved instruction provided by the fetch logic; and
scheduler logic for scheduling the retrieved instruction for execution, the scheduler logic including a buffer for storing the retrieved instruction and one or more additional instructions,
the scheduler logic further comprising:
a checkpointed version of the buffer comprising an instruction causing entry into runahead and a plurality of subsequent instructions; and
a non-checkpointed version of the buffer operating in a working state to speculatively execute an unlimited number of instructions during runahead;
wherein, after runahead, the scheduler logic is configured to reset the buffer to the checkpointed version,

wherein the scheduler logic is configured, upon the microprocessor re-entering at a particular execution location after runahead, to re-dispatch, from the buffer, an instruction that has been previously dispatched to one of the execution mechanisms.

2. The microprocessor of claim 1 , wherein the buffer is stored in a single array comprising 2N entries of the retrieved instructions arranged in pairs.

3. The microprocessor of claim 2 , wherein the scheduler logic comprises an address bit configured to identify whether a selected address for a selected entry in storage cells corresponds to a checkpointed version of the buffer or a non-checkpointed version of the buffer.

4. The microprocessor of claim 1 , wherein the buffer comprises:
a read pointer for reading a selected instruction held in the buffer in preparation for dispatching the selected instruction for execution; and
a de-allocation pointer for causing the selected instruction to be logically removed from the buffer after the selected instruction completes.

5. The microprocessor of claim 4 , wherein the buffer further comprises:
a replay pointer for causing a selected instruction to be re-dispatched for re-execution during replay; and
a restart instruction pointer for tracking an address following a last complete instruction held in the buffer, the restart instruction pointer directing an instruction pointer for the fetch logic wherein the fetch logic fetches another instruction from outside of the buffer while the selected instruction is re-dispatched for re-execution.

6. The microprocessor of claim 1 , wherein the buffer is configured to store a plurality of bundles of micro-operations, each micro-operation corresponding to one or more instruction set architecture (ISA) instructions or parts of ISA instructions, wherein the scheduler logic further comprises a boundary instruction pointer for tracking a boundary between a last bundle for a complete ISA instruction held in the buffer and a subsequent bundle belonging to an incomplete ISA instruction held in the buffer, and wherein the restart instruction pointer is configured to track an address following a last complete instruction held in the buffer as tracked by the boundary instruction pointer.

7. The microprocessor of claim 1 , wherein the checkpointed version is generated by the scheduler logic upon entry into runahead.

8. The microprocessor of claim 7 , wherein the checkpointed version comprises one or more vacancies.

9. The microprocessor of claim 1 , wherein the fetch logic and the scheduler logic are upstream of a pipeline of the microprocessor.

10. The microprocessor of claim 1 , wherein the scheduler logic is included in the fetch logic and/or decode logic for decoding an instruction for execution at one of the execution mechanisms of the microprocessor.

11. A method for re-dispatching an instruction to be re-executed at a microprocessor, the method comprising:
entering a runahead condition;
generating a checkpointed version of a buffer, wherein the checkpointed version comprises an instruction causing entry into runahead and a plurality of subsequent instructions;
reading an instruction selected for re-execution upon the microprocessor re-entering a particular execution location after returning from the runahead condition, the instruction held in the buffer during the runahead condition for re-dispatch to one or more execution mechanisms of the microprocessor,
wherein said buffer is within scheduler logic of the microprocessor;
after returning from the runahead condition, re-dispatching the instruction; and
from outside of the buffer, fetching another instruction while the selected instruction is re-executed.

12. The method of claim 11 , further comprising, after runahead and before reading the instruction held in the buffer, resetting a non-checkpointed version of the buffer to the checkpointed version.

13. The method of claim 12 , wherein the resetting the non-checkpointed version of the buffer to the checkpointed version comprises:
copying a checkpointed version of a de-allocation pointer to a read pointer, the de-allocation pointer configured to cause the instruction to be logically removed from the buffer after the selected instruction completes, wherein the read pointer is configured to read the instruction in preparation for execution; and
copying the checkpointed version of the de-allocation pointer to a replay pointer, the replay pointer configured to cause a selected instruction to be re-dispatched for re-execution during replay.

14. The method of claim 13 , wherein the re-dispatching the instruction comprises: reading the instruction as indicated by the read pointer dispatching the instruction to the one or more execution mechanisms; and
logically removing the instruction from the buffer upon completion as indicated by the de-allocation pointer.

15. The method of claim 14 , wherein the re-dispatching the instruction further comprises replaying the instruction as indicated by the replay pointer responsive to an execution stall.

16. The method of claim 14 , wherein the fetching another instruction from outside the buffer comprises copying a restart instruction pointer to an instruction pointer for fetch logic of the microprocessor wherein the fetch logic fetches the other instruction from outside of the buffer while the instruction is re-executed, wherein further the restart instruction pointer is configured to track an address following a last complete instruction held in the buffer.

17. The method of claim 16 , wherein the buffer is configured to store a plurality of bundles of micro-operations, each micro-operation corresponding to one or more ISA instructions or parts of ISA instructions, wherein the restart instruction pointer is configured to track an address following a last complete instruction held in the buffer with reference to a boundary instruction pointer configured to track a boundary between a last bundle for a complete ISA instruction held in the buffer and a subsequent bundle belonging to an incomplete ISA instruction held in the buffer, and wherein the fetching another instruction from outside the buffer comprises tracking a boundary between a last bundle for a complete ISA instruction held in the buffer and a subsequent bundle belonging to an incomplete ISA instruction held in the buffer with the boundary instruction pointer.

18. A microprocessor configured to break an ISA instruction into a plurality of micro-instructions for execution, the microprocessor comprising:
scheduler logic comprising:
a buffer for storing a plurality of bundles of micro-operations in a checkpointed state during runahead, each micro-operation corresponding to one or more ISA instructions held in the buffer for dispatch to an ex

Assignees

• Rozas Guillermo J
• Serris Paul
• Hoyt Brad
• Ramakrishnan Sridharan
• Vanderschoot Hens
• Segelken Ross
• Boggs Darrell
• Ekman Magnus
• Nvidia Corp

Inventors

• Rozas Guillermo J
• Serris Paul
• Hoyt Brad
• Ramakrishnan Sridharan
• Vanderschoot Hens
• Segelken Ross
• Boggs Darrell
• Ekman Magnus

Classifications

• G06F9/3814

  Implementation provisions of instruction buffers, e.g. prefetch buffer; banks · CPC title

• G06F9/3863

  using multiple copies of the architectural state, e.g. shadow registers · CPC title

• G06F9/3802 Primary

  Instruction prefetching · CPC title