Three-dimensional memory device including a string selection line gate electrode having a silicide layer

Patent metadata

Field	Value
Publication number	US-11374017-B2
Application number	US-202016842055-A
Country	US
Kind code	B2
Filing date	Apr 7, 2020
Priority date	Sep 24, 2019
Publication date	Jun 28, 2022
Grant date	Jun 28, 2022

Abstract

A three-dimensional memory device is provided. The three-dimensional memory device may include a substrate, a cell stack, a string selection line gate electrode, a lower vertical channel structure, an upper vertical channel structure, and a bit line. The string selection line gate electrode may include a lower string selection line gate electrode and an upper string selection line gate electrode formed on an upper surface of the lower string selection line gate electrode. The lower string selection line gate electrode may include N-doped poly-crystalline silicon. The upper string selection line gate electrode may include silicide.

First claim

What is claimed is:

1. A three-dimensional memory device, comprising:
a substrate;
a cell stack disposed on the substrate;
a string selection line gate electrode disposed on the cell stack;
a string selection line separation pattern formed on a sidewall of the string selection line gate electrode;
a lower vertical channel structure vertically penetrating the cell stack;
an upper vertical channel structure vertically penetrating the string selection line gate electrode and being connected to the lower vertical channel structure; and
a bit line disposed on the upper vertical channel structure,
wherein the string selection line gate electrode includes a lower string selection line gate electrode and an upper string selection line gate electrode formed on an upper surface of the lower string selection line gate electrode,
the lower string selection line gate electrode includes N-doped poly-crystalline silicon, and
the upper string selection line gate electrode includes silicide, and
the string selection line separation pattern is in direct contact with a sidewall of the lower string selection line gate electrode and a sidewall of the upper string selection line gate electrode.

2. The device of claim 1 , wherein
the lower vertical channel structure includes:
a lower gap-fill pattern;
a lower channel layer surrounding a sidewall of the lower gap-fill pattern; and
a memory layer surrounding a sidewall of the lower channel layer,
the upper vertical channel structure includes:
an upper gap-fill pattern;
an upper channel layer surrounding a sidewall of the upper gap-fill pattern; and
an insulating liner surrounding a sidewall of the upper channel layer, and
the upper vertical channel structure includes a lower portion having a first width and an upper portion having a second width, with the first width larger than the second width.

3. The device of claim 2 , wherein the upper channel layer includes:
a first upper channel layer being in contact with the insulating liner;
a second upper channel layer being in contact with the memory layer of the lower vertical channel structure; and
a third upper channel layer being in contact with the lower gap-fill pattern of the lower vertical channel structure.

4. The device of claim 3 , wherein
the first upper channel layer and the second upper channel layer extend vertically, and
the third upper channel layer extends horizontally.

5. The device of claim 4 , wherein the lower channel layer and the second upper channel layer are vertically aligned.

6. The device of claim 3 , wherein the upper gap-fill pattern includes:
an upper portion surrounded by the first upper channel layer; and
a lower portion surrounded by the second upper channel layer,
wherein the upper portion of the upper gap-fill pattern has a third width narrower than a fourth width of the lower portion of the upper gap-fill pattern.

7. The device of claim 6 , further comprising a void formed in the lower portion of the upper gap-fill pattern.

8. The device of claim 3 , wherein the third upper channel layer is disposed between the lower gap-fill pattern and the upper gap-fill pattern.

9. The device of claim 2 , further comprising a pad pattern disposed between the upper vertical channel structure and the bit line,
wherein the pad pattern includes a lower pad pattern including N-doped poly-crystalline silicon and an upper pad pattern including silicide.

10. The device of claim 9 , wherein the bit line is in direct contact with the upper pad pattern.

11. The device of claim 9 , wherein an outer surface of the pad pattern and an outer surface of the upper channel layer are vertically aligned.

12. The device of claim 2 , wherein
the lower vertical channel structure includes a protruding portion protruding into the substrate,
the lower vertical channel structure further includes a bottom memory layer disposed at the protruding portion, and
the bottom memory layer is separate from the memory layer.

13. The device of claim 1 , wherein the upper string selection line gate electrode includes:
a protruding portion located adjacent to the upper vertical channel structure; and
a recessed portion spaced apart from the upper vertical channel structure,
wherein the protruding portion has a disk shape in a plan view.

14. The device of claim 1 , further comprising a common source layer disposed between the substrate and the cell stack,
wherein the common source layer includes N-doped poly-crystalline silicon.

15. The device of claim 14 , further comprising a logic circuit layer disposed between the substrate and the common source layer,
wherein the logic circuit layer includes a transistor, a metal interconnection, and a lower insulating layer covering the transistor and the metal interconnection.

16. The device of claim 14 , wherein the common source layer is connected to the substrate.

17. A three-dimensional memory device comprising:
a substrate;
a common source layer disposed on the substrate;
a cell stack disposed on the common source layer;
a string selection line gate electrode disposed on the cell stack;
a lower vertical channel structure vertically penetrating the cell stack and being connected to the common source layer;
an upper vertical channel structure vertically penetrating the string selection line gate electrode and being connected to the lower vertical channel structure;
a pad pattern disposed on the upper vertical channel structure; and
a bit line disposed on the pad pattern,
wherein the pad pattern includes a lower pad pattern and an upper pad pattern formed on the lower pad pattern,
the lower pad pattern includes N-doped poly-crystalline silicon, and
the upper pad pattern includes silicide.

18. The device of claim 17 , wherein
the string selection line gate electrode includes a lower string selection line gate electrode and an upper string selection line gate electrode formed on the lower string selection line gate electrode,
the lower string selection line gate electrode includes N-doped poly-crystalline silicon, and
the upper string selection line gate electrode includes silicide.

19. A three-dimensional memory device comprising:
a substrate;
a logic circuit layer disposed on the substrate, the logic circuit layer including a transistor, a metal interconnection, and a lower insulating layer covering the transistor and the metal interconnection;
a common source layer disposed on the logic circuit layer;
a cell stack disposed on the common source layer;
a lower vertical channel structure vertically penetrating the cell stack and being connected to the common source layer;
a string selection line gate electrode disposed on the cell stack and the lower vertical channel structure;
an upper vertical channel structure vertically penetrating the string selection line gate electrode and being connected to the lower vertical channel structure;
a pad pattern disposed on the upper vertical channel structure; and
a bit line disposed on the pad pattern,
wherein the pad pattern includes a lower pad pattern and an upper pad pattern formed on the lower pad pattern,
the string selection line gate electrode includes a lower string selection line gate electrode and an upper string selection line gate electrode formed on the lower string selection line gate electrode,
the lower pad pattern and the lower string selection line gate electrode include N-doped poly-crystalline silicon, and
the upper pad pattern and the upper string selection line gate electrode

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kanamori Kohji
• Kang Seogoo
• Ahn Jongseon
• Han Jeehoon

Classifications

• H10D64/0131

  the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation · CPC title

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D64/663

  the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates · CPC title

• H01L27/11524

  Electricity · mapped topic