Component and method of manufacturing a component using an ultrathin carrier

US11367654B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11367654-B2
Application numberUS-201916248255-A
CountryUS
Kind codeB2
Filing dateJan 15, 2019
Priority dateJul 5, 2012
Publication dateJun 21, 2022
Grant dateJun 21, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A system and method for manufacturing a packaged component are disclosed. An embodiment comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions. The method further comprises generating the component by separating the carrier.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for manufacturing a component, the method comprising: forming a plurality of components disposed on a front side of a first carrier comprising a semiconductor substrate, the plurality of components being separated from each other by kerf regions; attaching the front side of the first carrier on a second carrier; forming a planar metal pattern on a backside of the first carrier, wherein the planar metal pattern covers the backside of the first carrier except over regions corresponding to the kerf regions, and wherein the planar metal pattern comprises free standing metal blocks separated by the regions corresponding to the kerf regions; removing the second carrier and placing the first carrier on a sawing foil; and separating the component from the first carrier, wherein forming the planar metal pattern comprises forming a metal seed layer and electro-plating a metal of the planar metal pattern on the metal seed layer, and forming an under-layer between the seed layer and a substrate of the component, wherein the under-layer comprises a metal adhesion layer and a metal barrier layer. 2. The method according to claim 1 , wherein the planar metal pattern comprises copper (Cu). 3. The method according to claim 1 , wherein the substrate of the component and the planar metal pattern comprises about the same thickness. 4. The method according to claim 1 , wherein the substrate of the component comprises a thickness of about 40 μm or less, and wherein the planar metal pattern comprises a thickness of about 20 μm or more. 5. The method according to claim 1 , wherein separating the component from the first carrier comprises laser cutting the first carrier along the regions. 6. A method for manufacturing a component, the method comprising: providing a first carrier with a first main surface at a front side of the first carrier and a second main surface at a backside of the first carrier; disposing a plurality of components at the front side of the first carrier; attaching the first main surface of the first carrier to a second carrier; forming a planar patterned metal layer over the second main surface of the first carrier, the planar patterned metal pattern comprising free standing metal blocks separated by spaces; removing the second carrier and placing the first carrier on a sawing foil; and separating the component from the first carrier along the spaces, wherein forming the planar patterned metal layer comprises forming a metal seed layer and plating a metal layer over the seed layer, and forming an under-layer between the metal seed layer and a substrate of the component, wherein the under-layer comprises a metal layer stack of aluminum and titanium, and wherein the seed layer comprises the same material as the planar patterned metal layer. 7. The method according to claim 6 , wherein the first carrier is thinned at the backside before the planar patterned metal layer is formed. 8. The method according to claim 6 , wherein forming the planar patterned metal layer comprises forming a photoresist over the seed layer. 9. The method according to claim 6 , wherein the substrate of the component comprises a thickness of about 40 μm or less, and wherein the planar patterned metal layer comprises a thickness of about 20 μm or more. 10. The method according to claim 6 , wherein separating the component from the first carrier comprises laser cutting the first carrier. 11. The method according to claim 6 , further comprising placing the component on a leadframe, and encapsulating the component and at least a portion of the leadframe. 12. The method according to claim 11 , wherein placing the component on the leadframe comprises wire bonding or clip bonding the component to the leadframe. 13. A method of manufacturing a wafer, the method comprising: forming kerf regions and chips on a first main surface of the wafer; forming a planar metal pattern on a second main surface of the wafer, wherein the planar metal pattern covers the second main surface of the wafer except over regions corresponding to the kerf regions, and wherein the planar metal pattern comprises free standing metal blocks separated by the regions corresponding to the kerf regions, wherein forming the planar metal pattern comprises forming a metal seed layer and electro-plating a metal of the planar metal pattern on the metal seed layer; and forming an under-layer between the seed layer and a substrate of the wafer, wherein the under-layer comprises a metal adhesion layer and a metal barrier layer. 14. The method according to claim 13 , wherein the planar metal pattern comprises copper (Cu). 15. The method according to claim 13 , wherein forming the planar metal pattern comprises forming the metal seed layer in a metal bath and patterning a photoresist over the seed layer.

Assignees

Inventors

Classifications

  • Encapsulations, e.g. protective coatings · CPC title

  • Die-attach connectors and bond wires · CPC title

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • Die-attach connectors and strap connectors · CPC title

  • Soldering or alloying · CPC title

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Frequently asked questions

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What does patent US11367654B2 cover?
A system and method for manufacturing a packaged component are disclosed. An embodiment comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corre…
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification H10P54/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 21 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).