Reduction of defects in wafer level chip scale package (wlcsp) devices

US2016276176A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016276176-A1
Application numberUS-201514927283-A
CountryUS
Kind codeA1
Filing dateOct 29, 2015
Priority dateMar 21, 2015
Publication dateSep 22, 2016
Grant date

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.

First claim

Opening claim text (preview).

1 . A method for assembling a wafer level chip scale processed (WLCSP) wafer, the wafer substrate having a front-side surface and an opposite back-side surface, a plurality of device die on the front-side surface, the plurality of device die having bond pads upon which ball-drop solder balls are defined, the method comprising: defining trenches in saw lanes, on the front-side surface, between each one of the plurality of device die, the trenches having a depth of a final device die thickness; filling the trenches and covering the front-side surface with a molding compound, the molding compound surrounding the solder balls on each one of the plurality of device die; back grinding the back-side surface of the wafer substrate to the depth of the final device die thickness; and sawing apart the wafer in the trenches filled with molding compound, so as to separate the plurality of device die into individual devices. 2 . The method as recited in claim 1 , wherein filling the trenches includes covering the solder balls with molding compound. 3 . The method as recited in claim 2 , further comprising grinding down the molding compound covering the solder balls until surfaces of the solder balls are exposed. 4 . The method as recited in claim 1 , wherein the back grinding further includes, relieving back-side surface stress with at least one of the following: chemical-mechanical polishing (CMP), dry polishing, plasma polishing. 5 . The method as recited in claim 1 , further comprising, applying a coating on the back-side surface of the wafer substrate prior to sawing apart the wafer substrate. 6 . The method as recited in claim 1 , wherein defining trenches in the saw lanes includes at least one of the following: plasma etching, laser grooving, or dicing-before-grinding (DbG). 7 . The method as recited claim 1 , further comprising, subjecting the wafer substrate to a reflow process, so as to break and remove any residual molding compound on the solder balls. 8 . The method as recited in claim 6 , wherein the reflow process follows the filling of the trenches. 9 . The method as recited in claim 1 , wherein sawing apart the wafer substrate is performed from the front-side surface or the backside surface. 10 . A method for assembling a wafer level chip scale processed (WLCSP) wafer, the wafer substrate having a front-side surface and an opposite back-side surface, the front-side surface having a layer of low-k material at a thickness, a plurality of device die on the front-side surface, the plurality of device die having bond pads upon which ball-drop solder balls are defined, the plurality of device die separated from one another by saw lanes, the method comprising: laser grooving trenches in the saw lanes, the laser grooving done to a depth of the thickness of the low-k material; filling the trenches and covering the front-side surface with a front-side molding compound, the molding compound surrounding the solder balls on each one of the plurality of device die, the front-side molding compound has a first thickness; performing a flux-clean and reflow to break and remove flash over the solder balls; back-grinding the back-side surface of the wafer substrate to about a depth of a finished device; making first cuts with a saw blade of a first kerf, sawing through the back-side surface of the wafer substrate in the saw lanes, almost substantially at the depth of the finished device; applying a back-side molding compound to the back-side surface of the wafer substrate, wherein the molding compound fills in the first cuts and covers the back-side surface of the wafer substrate, the back-side molding compound has a second thickness; and making second cuts with a saw blade of a second kerf, the second cuts are at a depth a combination of the thickness of the finished device, the first thickness of the front-side molding compound, and the second thickness of the back-side molding compound, thereby separating the plurality of device die into individual devices, the individual devices having molding compound on vertical faces and on front-side and back-side surfaces. 11 . The method as recited in claim 10 , wherein the laser grooving has a width of about three-fourths of a width of a saw lane. 12 . The method as recited in claim 10 , wherein the first thickness of the front-side molding compound is comparable to the second thickness of the back-side molding compound. 13 . The method as recited in claim 10 , wherein the first kerf is greater than the second kerf.

Assignees

Inventors

Classifications

  • batch processes · CPC title

  • for identification or tracking · CPC title

  • comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

  • relative to the surface, e.g. recessed, protruding · CPC title

  • by reflowing · CPC title

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Frequently asked questions

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What does patent US2016276176A1 cover?
Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, …
Who is the assignee on this patent?
Nxp Bv
What technology area does this patent fall under?
Primary CPC classification H10W74/129. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Sep 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).