Electronic device with redistribution layer and stiffeners and related methods

Patent metadata

Field	Value
Publication number	US-2016104656-A1
Application number	US-201514741535-A
Country	US
Kind code	A1
Filing date	Jun 17, 2015
Priority date	Oct 11, 2014
Publication date	Apr 14, 2016
Grant date	—

Abstract

An electronic device may include an integrated circuit (IC), electrically conductive connectors coupled to the IC, and a heat sink layer adjacent the IC and opposite the electrically conductive connectors. The electronic device may include an encapsulation material surrounding the IC and the electrically conductive connectors, a redistribution layer having electrically conductive traces coupled to the electrically conductive connectors, a stiffener between the heat sink layer and the redistribution layer, and a fan-out component between the heat sink layer and the redistribution layer and being in the encapsulation material.

First claim

That which is claimed is:

1 . An electronic device comprising:
an integrated circuit (IC); a plurality of electrically conductive connectors coupled to said IC; a heat sink layer adjacent said IC and opposite said plurality of electrically conductive connectors; an encapsulation material surrounding said IC and said plurality of electrically conductive connectors; a redistribution layer having a plurality of electrically conductive traces coupled to said plurality of electrically conductive connectors; a stiffener between said heat sink layer and said redistribution layer; and a fan-out component between said heat sink layer and said redistribution layer and being in said encapsulation material.

2 . The electronic device of claim 1 further comprising a thermal interface layer between said heat sink layer and said IC.

3 . The electronic device of claim 1 further comprising a plurality of electrically conductive solder balls coupled to said redistribution layer.

4 . The electronic device of claim 1 wherein said stiffener has an inner surface adjacent said encapsulation material and an outer surface defining an external surface of the electronic device.

5 . The electronic device of claim 1 wherein said stiffener abuts said encapsulation material.

6 . The electronic device of claim 1 wherein said redistribution layer comprises a dielectric layer; and wherein said plurality of electrically conductive traces is carried by said dielectric layer and coupled to said plurality of electrically conductive connectors.

7 . The electronic device of claim 1 wherein said fan-out component comprises a ceramic material.

8 . The electronic device of claim 1 wherein said plurality of electrically conductive connectors comprises at least one of a solder bump and a pillar.

9 . An electronic device comprising:
an integrated circuit (IC); a plurality of electrically conductive connectors coupled to said IC; a heat sink layer adjacent said IC and opposite said plurality of electrically conductive connectors; a thermal interface layer between said heat sink layer and said IC; an encapsulation material surrounding said IC and said plurality of electrically conductive connectors; a redistribution layer having a plurality of electrically conductive traces coupled to said plurality of electrically conductive connectors; a stiffener between said heat sink layer and said redistribution layer and having an inner surface adjacent said encapsulation material and an outer surface defining an external surface of the electronic device; and a fan-out component between said heat sink layer and said redistribution layer and being in said encapsulation material.

10 . The electronic device of claim 9 further comprising a plurality of electrically conductive solder balls coupled to said redistribution layer.

11 . The electronic device of claim 9 wherein said stiffener abuts said encapsulation material.

12 . The electronic device of claim 9 wherein said redistribution layer comprises a dielectric layer; and wherein said plurality of electrically conductive traces is carried by said dielectric layer and coupled to said plurality of electrically conductive connectors.

13 . The electronic device of claim 9 wherein said fan-out component comprises a ceramic material.

14 . The electronic device of claim 9 wherein said plurality of electrically conductive connectors comprises at least one of a solder bump and a pillar.

15 . A method of making an electronic device comprising:
forming a plurality of electrically conductive connectors coupled to an integrated circuit (IC); positioning a heat sink layer adjacent the IC and opposite the plurality of electrically conductive connectors; forming an encapsulation material surrounding the IC and the plurality of electrically conductive connectors; positioning a redistribution layer having a plurality of electrically conductive traces coupled to the plurality of electrically conductive connectors; positioning a stiffener between the heat sink layer and the redistribution layer; and positioning a fan-out component between the heat sink layer and the redistribution layer and being in the encapsulation material.

16 . The method of claim 15 further comprising forming a thermal interface layer between the heat sink layer and the IC.

17 . The method of claim 15 further comprising forming a plurality of electrically conductive solder balls coupled to the redistribution layer.

18 . The method of claim 15 wherein the stiffener has an inner surface adjacent the encapsulation material and an outer surface defining an external surface of the electronic device.

19 . The method of claim 15 wherein the stiffener abuts the encapsulation material.

20 . The method of claim 15 wherein the redistribution layer comprises a dielectric layer; and wherein the plurality of electrically conductive traces is carried by the dielectric layer and coupled to the plurality of electrically conductive connectors.

21 . The method of claim 15 wherein the fan-out component comprises a ceramic material.

22 . The method of claim 15 wherein the plurality of electrically conductive connectors comprises at least one of a solder bump and a pillar.

Assignees

• St Microelectronics Pte Ltd

Inventors

• Luan Jing-En

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title