Embedded pad structures of three-dimensional memory devices and fabrication methods thereof

Patent metadata

Field	Value
Publication number	US-10930661-B2
Application number	US-201816163274-A
Country	US
Kind code	B2
Filing date	Oct 17, 2018
Priority date	Aug 16, 2018
Publication date	Feb 23, 2021
Grant date	Feb 23, 2021

Abstract

Embodiments of 3D memory devices and fabricating methods thereof are disclosed. The device comprises an array device semiconductor structure comprising an array interconnect layer disposed on the alternating conductor/dielectric stack and including a first interconnect structure. The device further comprises a peripheral device semiconductor structure comprising a peripheral interconnect layer disposed on a peripheral device and including a second interconnect structure. The device further comprises a pad embedded in the array device semiconductor structure or the peripheral interconnect layer, and a pad opening exposing a surface of the pad. The array interconnect layer is bonded with the peripheral interconnect layer, and the pad is electrically connected with the peripheral device through the first interconnect structure or the second interconnect structure.

First claim

What is claimed is:

1. A 3D memory device, comprising:
an array device semiconductor structure comprising:
an alternating conductor/dielectric stack disposed on a semiconductor layer, and
an array interconnect layer disposed on the alternating conductor/dielectric stack and including at least one first interconnect structure;

a peripheral device semiconductor structure comprising:
at least one peripheral device disposed on a substrate, and
a peripheral interconnect layer disposed on the at least one peripheral device and including at least one second interconnect structure;

at least one pad embedded in the array device semiconductor structure or the peripheral interconnect layer; and
a pad opening exposing a surface of the at least one pad;
wherein the array interconnect layer is bonded with the peripheral interconnect layer, and the at least one pad is electrically connected with the at least one peripheral device through the at least one first interconnect structure or the at least one second interconnect structure.

2. The device of claim 1 , wherein:
the at least one pad is embedded in the peripheral interconnect layer;
the pad opening extends through the array device semiconductor structure and extends into the peripheral interconnect layer; and
the at least one pad is electrically connected with the at least one peripheral device through at least one second interconnect structure.

3. The device of claim 1 , wherein:
the at least one pad is embedded in the array interconnect layer;
a depth of the pad opening is larger than a thickness of the alternating conductor/dielectric stack; and
the at least one pad is electrically connected with at least one peripheral device through the at least one first interconnect structure and the at least one second interconnect structure.

4. The device of claim 1 , wherein:
the at least one pad is embedded in a dielectric layer and is sandwiched between a first lateral surface coplanar with a top surface of the alternating conductor/dielectric stack and a second lateral surface coplanar with a bottom surface of the alternating conductor/dielectric stack;
a depth of the pad opening is less than a thickness of the alternating conductor/dielectric stack; and
the at least one pad is electrically connected with at least one peripheral device through at least one pad interconnect structure in the dielectric layer, the at least one first interconnect structure, and the at least one second interconnect structure.

5. The device of claim 3 , wherein the at least one pad is located at a side edge of the alternating conductor/dielectric stack and close to a staircase structure region.

6. The device of claim 3 , wherein:
the at least one pad is located in a dielectric layer in the array interconnect layer; and
the pad opening extends through the alternating conductor/dielectric stack.

7. The device of claim 6 , wherein:
the at least one pad is located in a dielectric structure that extends through the alternating conductor/dielectric stack.

8. The device of claim 7 , wherein:
the dielectric structure is isolated from the alternating conductor/dielectric stack by a barrier structure.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Chen Jun
• Xia Zhiliang
• Xiao li hong

Classifications

• H01L27/11573 Primary

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/40 Primary

  characterised by the peripheral circuit region · CPC title