Multi-tier three-dimensional memory devices including vertically shared source lines and method of making thereof

Patent metadata

Field	Value
Publication number	US-9935050-B2
Application number	US-201715634423-A
Country	US
Kind code	B2
Filing date	Jun 27, 2017
Priority date	Aug 25, 2015
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

A multi-tier memory device includes a first tier structure overlying a substrate and containing a first alternating stack of first insulating layers and first electrically conductive layers, and first memory stack structures each including a first memory film and a first vertical semiconductor channel, a source line overlying the first tier structure, and a second tier structure overlying the source line and containing a second alternating stack of second insulating layers and second electrically conductive layers, and second memory stack structures each including a second memory film and a second vertical semiconductor channel.

First claim

What is claimed is:

1. A multi-tier memory device, comprising:
a first tier structure overlying a substrate and comprising a first alternating stack of first insulating layers and first electrically conductive layers, and first memory stack structures each including a first memory film and a first vertical semiconductor channel;
a source line overlying the first tier structure; and
a second tier structure overlying the source line and comprising a second alternating stack of second insulating layers and second electrically conductive layers, and second memory stack structures each including a second memory film and a second vertical semiconductor channel.

2. The multi-tier memory device of claim 1 , wherein:
each first vertical semiconductor channel is located within a respective first memory stack structure that extends through the first alternating stack; and
each second vertical semiconductor channel is located within a respective second memory stack structure that extends through the second alternating stack.

3. The multi-tier memory device of claim 1 , wherein the source line is a shared buried source line which is electrically shorted to top ends of the first vertical semiconductor channels in the first tier structure and to bottom ends of the second vertical semiconductor channels in the second tier structure.

4. The multi-tier memory device of claim 3 , further comprising:
a dielectric material layer overlying the substrate;
first bit lines embedded within the dielectric material layer;
first-tier drain regions that contact a lower end of a respective first vertical semiconductor channel and electrically shorted to a respective one of the first bit lines;
second bit lines overlying the second tier structure; and
second-tier drain regions that contact an upper end of a respective second vertical semiconductor channel and electrically shorted to a respective one of the second bit lines.

5. The multi-tier memory device of claim 4 , further comprising first source regions contacting a respective one of the first semiconductor channels and a bottom surface of the source line.

6. The multi-tier memory device of claim 1 , further comprising first bit lines located between the first tier structure and the second tier structure, wherein the source line is a buried source line which is electrically shorted to bottom ends of the second vertical semiconductor channels in the second tier structure.

7. The multi-tier memory device of claim 6 , further comprising:
a first source region located in the substrate, wherein each of the first semiconductor channels is connected to the first source region directly or through a horizontal channel in the substrate;
first bit lines overlying the first tier structure;
first-tier drain regions that contact an upper end of the respective first vertical semiconductor channel and electrically shorted to a respective one of the first bit lines;
second bit lines overlying the second tier structure; and
second-tier drain regions that contact an upper end of the respective second vertical semiconductor channel and electrically shorted respective one of the second bit lines.

8. The multi-tier memory device of claim 7 , further comprising:
a source contact via structure extending through the first alternating stack and in contact with the first source region; and
at least one inter-tier dielectric material layer embedding the first bit lines and the source line, wherein the source line is located above the first bit lines.

9. The multi-tier memory device of claim 1 , further comprising:
a first terrace region in which each first electrically conductive layer other than a topmost first electrically conductive layer laterally extends farther than an overlying first electrically conductive layer;
a first retro-stepped dielectric material portion overlying the first terrace region;
first control gate contact via structures extending through the first retro-stepped dielectric material portion;
first control gate interconnect lines located below the second alternating stack and contacting a respective one of the first control gate contact via structures;
a second terrace region in which each second electrically conductive layer other than a topmost second electrically conductive layer laterally extends farther than an overlying second electrically conductive layer;
a second retro-stepped dielectric material portion overlying the second terrace region;
second control gate contact via structures extending through the second retro-stepped dielectric material portion; and
second control gate interconnect lines located above the second alternating stack and contacting a respective one of the second control gate contact via structures,
wherein a predominant portion of an entire area of the second terrace region overlaps with an area of the first terrace region.

10. The multi-tier memory device of claim 1 , wherein:
the multi-tier memory device comprises a vertical NAND device located over the substrate;
the first and second electrically conductive layers comprise, or are electrically connected to, a respective word line of the vertical NAND device;
the substrate comprises a silicon substrate; and
the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate.

11. A method of manufacturing a multi-tier memory device, comprising:
forming a first alternating stack of first insulating layers and first spacer material layers over a substrate, wherein the first spacer material layers are formed as, or are subsequently replaced with, first electrically conductive layers;
forming first memory stack structures through the first alternating stack, wherein each first memory stack structure comprises a first memory film and a first semiconductor channel;
forming a source line over the first tier structure;
forming a second alternating stack of second insulating layers and second spacer material layers over the source line, wherein the second spacer material layers are formed as, or are subsequently replaced with, second electrically conductive layers; and
forming second memory stack structures through the second alternating stack, wherein each second memory stack structure comprises a second memory film and a second semiconductor channel.

12. The method of claim 11 , further comprising:
forming first bit lines embedded within a dielectric material layer over the substrate;
forming first-tier drain regions that are electrically shorted to a respective one of the first bit lines and located over the first bit lines, wherein bottoms of the first semiconductor channels are electrically shorted to the respective first-tier drain region;
forming second bit lines over the second memory stack structures; and
forming second-tier drain regions on upper ends of the second semiconductor channels and electrically shorted to a respective one of the second bit lines.

13. The method of claim 12 , further comprising forming first source regions directly on a respective one of the first semiconductor channels, wherein the source line is formed on the first source regions.

14. The method of claim 12 , further comprising forming first drain contact via structures in the dielectric material layer and directly a top surface of a respective one of the first bit lines, wherein the first semiconductor channels are formed over the first drain contact via structures.

15. The method of claim 12 , wherein the second semiconductor channels are formed directly on the source line.

16. The method of claim 11 , further comp

Assignees

• Sandisk Technologies Llc

Inventors

• Dunga Mohan
• Mizutani Yuki
• Lu Zhenyu

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title