Semiconductor packages

Patent metadata

Field	Value
Publication number	US-11355445-B2
Application number	US-202017007945-A
Country	US
Kind code	B2
Filing date	Aug 31, 2020
Priority date	Dec 26, 2019
Publication date	Jun 7, 2022
Grant date	Jun 7, 2022

Abstract

A semiconductor package includes a lower connection structure, a semiconductor chip on the lower connection structure, an upper connection structure including a first conductive pattern layer on the semiconductor chip, a first insulating layer on the first conductive pattern layer, a second conductive pattern layer on the first insulating layer, a first via penetrating the first insulating layer to extend between the first conductive pattern layer and the second conductive pattern layer, and a second insulating layer extending between a side surface of the first via and the first insulating layer, and an intermediate connection structure between the lower connection structure and the upper connection structure. A chemical composition of the first insulating layer may differ from a chemical composition of the second insulating layer.

First claim

What is claimed is:

1. A semiconductor package comprising:
a lower connection structure;
a semiconductor chip on the lower connection structure;
an upper connection structure comprising a first conductive pattern layer on the semiconductor chip, a first insulating layer on the first conductive pattern layer, a second conductive pattern layer on the first insulating layer, a first via penetrating the first insulating layer to extend between the first conductive pattern layer and the second conductive pattern layer, and a second insulating layer extending between a side surface of the first via and the first insulating layer; and
an intermediate connection structure between the lower connection structure and the upper connection structure,
wherein the semiconductor chip is between the upper connection structure and the lower connection structure, and the lower connection structure comprises a lower insulating layer on a lower surface of the semiconductor chip and on a lower surface of the intermediate connection structure, the lower connection structure further comprising a lower conductive pattern layer on the lower insulating layer, which is connected to the semiconductor chip and the intermediate connection structure by way of separate lower vias, respectively, and
wherein a chemical composition of the first insulating layer differs from a chemical composition of the second insulating layer.

2. The semiconductor package of claim 1 , wherein the second insulating layer further extends between the second conductive pattern layer and the first insulating layer.

3. The semiconductor package of claim 1 , wherein the chemical composition of the first insulating layer comprises a matrix and a filler in the matrix, and
wherein the chemical composition of the second insulating layer is free of the filler.

4. The semiconductor package of claim 1 , wherein a portion of the first conductive pattern layer is configured to be grounded, and
wherein a portion of the second conductive pattern layer is configured to transmit signals.

5. The semiconductor package of claim 4 , wherein the entire first conductive pattern layer is configured to be grounded.

6. The semiconductor package of claim 4 , wherein the portion of the first conductive pattern layer that is configured to be grounded is a first portion, and
wherein the first conductive pattern layer further comprises a second portion that is configured to transmit signals.

7. The semiconductor package of claim 4 , wherein the portion of the second conductive pattern layer that is configured to transmit signals is a first portion,
wherein the second conductive pattern layer further comprises a second portion that is configured to be grounded, and
wherein the portion of the first conductive pattern layer is configured to be grounded through the first via and the second portion of the second conductive pattern layer.

8. The semiconductor package of claim 1 , wherein the first conductive pattern layer is indirectly electrically connected to the intermediate connection structure by the second conductive pattern layer.

9. A semiconductor package comprising:
a lower semiconductor package;
an upper semiconductor package on the lower semiconductor package; and
an inter-package connection member between the lower semiconductor package and the upper semiconductor package,
wherein the lower semiconductor package comprises:
a first connection structure;
a first semiconductor chip on the first connection structure;
a second connection structure on the first connection structure; and
a third connection structure comprising a first conductive pattern layer on the first semiconductor chip, a first insulating layer on the first conductive pattern layer and the second connection structure, a second conductive pattern layer on the first insulating layer, a first via penetrating the first insulating layer, and a second insulating layer extending between a side surface of the first via and the first insulating layer,
wherein a chemical composition of the first insulating layer differs from a chemical composition of the second insulating layer,
wherein the first semiconductor chip is between the first connection structure and the third connection structure, and the first connection structure comprises a lower insulating layer on a lower surface of the first semiconductor chip and on a lower surface of the second connection structure, the first connection structure further comprising a lower conductive pattern layer on the lower insulating layer, which is connected to the semiconductor chip and the second connection structure by way of separate lower vias, respectively,
wherein the upper semiconductor package includes a fourth connection structure and a second semiconductor chip on the fourth connection structure, and
wherein the inter-package connection member is between the second conductive pattern layer of the third connection structure and the fourth connection structure.

10. The semiconductor package of claim 9 , wherein the first via extends between the first conductive pattern layer and the second conductive pattern layer.

11. The semiconductor package of claim 9 , wherein the lower semiconductor package further comprises a sealing layer between the first insulating layer and the second connection structure, and
wherein the third connection structure further comprises a second via penetrating the first insulating layer and the sealing layer to extend between the second conductive pattern layer and the second connection structure.

12. The semiconductor package of claim 11 , wherein the second insulating layer further extends between a side surface of the second via and the first insulating layer and between a side surface of the second via and the sealing layer.

13. The semiconductor package of claim 11 , wherein the first conductive pattern layer is indirectly connected to the second connection structure by the second via.

14. The semiconductor package of claim 9 , wherein the lower semiconductor package further comprises a sealing layer between the first insulating layer and the second connection structure, and
wherein the third connection structure further comprises a third via penetrating the sealing layer to extend between the first conductive pattern layer and the second connection structure.

15. The semiconductor package of claim 14 , wherein the second insulating layer does not directly contact the third via.

16. The semiconductor package of claim 9 , wherein the lower semiconductor package further comprises a protective layer, and
wherein the second conductive pattern layer comprises a first portion on which the protective layer is disposed and a second portion in contact with the inter-package connection member.

17. A semiconductor package comprising:
a semiconductor chip;
an intermediate connection structure comprising an intermediate insulating layer on sides of the semiconductor chip and an intermediate via penetrating the intermediate insulating layer;
a lower connection structure comprising a lower insulating layer on a lower surface of the semiconductor chip and on a lower surface of the intermediate connection structure and a lower conductive pattern layer on the lower insulating layer and connected to the semiconductor chip and the intermediate via;
a sealing layer on an upper surface of the semiconductor chip and an upper surface of the intermediate connection structure;
an upper connection structure including a first upper conductive pattern layer on the sealing layer, a first upper insulating layer o

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Joonsung
• Lee Doohwan
• Ko Taeho
• Kim Bongsoo
• Park Seokbong

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/851

  Dispositions of multiple connectors or interconnections · CPC title