Wafer scale supercomputer

Patent metadata

Field	Value
Publication number	US-11335657-B2
Application number	US-202017023297-A
Country	US
Kind code	B2
Filing date	Sep 16, 2020
Priority date	Sep 16, 2020
Publication date	May 17, 2022
Grant date	May 17, 2022

Abstract

A data processing system includes a first wafer comprising a plurality of first chips, and kerf and crack-stop structures around perimeters of the first chips, and a second wafer comprising a plurality second chips, a plurality of interconnect structures through a connection zone between the second chips, and a plurality of thru silicon vias, wherein the first wafer and the second wafer are bonded face-to-face such that the interconnect structures of the second wafer electrically connect adjacent chip sites of the first wafer and where a pitch of the chips on the first and second wafer are equal.

First claim

What is claimed is:

1. A data processing system comprising:
a first wafer comprising a plurality of first chips, and kerf and crack-stop structures around perimeters of the first chips; and
a second wafer comprising a plurality second chips, a plurality of interconnect structures through a connection zone between the second chips, and a plurality of thru silicon vias,
wherein the first wafer and the second wafer are bonded face-to-face such that the interconnect structures of the second wafer electrically connect adjacent chip sites of the first wafer and where a pitch of the chips on the first and second wafer are equal.

2. The data processing system of claim 1 , wherein the second wafer comprises two or more corresponding laminate wiring substrates attached to solder bumps connecting to the thru silicon vias.

3. The data processing system of claim 1 , wherein the kerf and crack-stop structures of the first wafer are formed around perimeters of the first chips in the connection zone, and wherein the second wafer does not include individual chip site crack-stop structures.

4. The data processing system of claim 1 , wherein the plurality of interconnect structures are terminated on an insulator surface layer of the second wafer.

5. The data processing system of claim 1 , wherein adjacent ones of the second chips of the second wafer disposed on different sides of the connection zone electrically connect to corresponding ones of the first chips of the first wafer and an indirect electrical connection is formed between adjacent ones of the first chips of the first wafer through the plurality of interconnect structures, and wherein the second chips of the second wafer are electrically connected by the plurality of interconnect structures.

6. The data processing system of claim 1 , wherein the second wafer is an interconnect wafer comprising at least one of a router logic, a power conversion device, a memory device, and a decoupling capacitor.

7. A computer system comprising:
a first wafer comprising a plurality of wafer-to-wafer interconnect structures terminated on a first insulator surface layer of the first wafer; and
a second wafer comprising a plurality of chip-to-chip interconnects disposed through a connection zone and terminated on a second insulator surface layer of the second wafer, and a plurality of thru silicon vias,
wherein the first wafer and the second wafer are bonded face-to-face such that the chip-to-chip interconnects of the second wafer are electrically connected to the wafer-to-wafer interconnect structures of the first wafer, and the chip-to-chip interconnects and the wafer-to-wafer interconnect structures electrically connect a plurality of chip sites of the first wafer and the second wafer, and
wherein the first wafer comprises kerf and crack-stop structures around perimeters of the chip sites of the first wafer in the connection zone.

8. The computer system of claim 7 , where the chip-to-chip interconnects of the second wafer electrically connect at least an adjacent pair of the chip sites of the first wafer.

9. The computer system of claim 7 , where the chip-to-chip interconnects of the second wafer electrically connect at least a non-adjacent pair of the chip sites of the first wafer.

10. The computer system of claim 7 , where the chip-to-chip interconnects and the wafer-to-wafer interconnect structures electrically connect at least one of the chips of the first wafer to at least one of the chips on the second wafer.

11. The computer system of claim 7 , further comprising a redistribution layer formed on at least one of a surface of the second wafer opposite the first wafer and a surface of the first wafer opposite the second wafer.

12. The computer system of claim 7 , further comprising a power supply electrically connected to at least one of the thru silicon vias, providing power to the first and the second wafers.

13. The computer system of claim 7 , wherein data input/output is communicated through at least one of the thru silicon vias.

14. The computer system of claim 7 , wherein a plurality of individual laminate wiring substrates are attached to the second wafer and having correspondence to the chip sites of the first wafer.

15. The computer system of claim 7 , wherein the chip-to-chip interconnects are arranged around a perimeter of chip sites of the second wafer.

16. The computer system of claim 7 , the face-to-face bonding achieves a simultaneous oxide-to-oxide and copper-to-copper connections between the chip sites of the first and second wafers, wherein the chip-to-chip interconnects and the wafer-to-wafer interconnect structures are formed of copper.

17. The computer system of claim 7 , wherein the second wafer does not include crack-stop structures and where a pitch of the chip sites on the first and second wafers are equal.

18. A data processing system comprising:
a first substrate comprising a plurality of first chips and comprising a plurality of wafer-to-wafer interconnect structures through a connection zone and terminated on a first insulator surface layer; and
a second substrate comprising a plurality of second chips and comprising a plurality of chip-to-chip interconnects terminated on a second insulator surface layer, and a plurality of thru silicon vias,
wherein the first substrate and the second substrate are bonded face-to-face such that the chip-to-chip interconnects of the second substrate are electrically connected to the wafer-to-wafer interconnect structures of the first substrate, and the wafer-to-wafer interconnect structures electrically connect opposing ones of the chips of the first and the second substrates,
wherein the first substrate comprises kerfs disposed with correspondence around the chip-to-chip interconnects of the seconds chips,
wherein the first substrate comprises crack-stop structures disposed within perimeters of the first chips, and
wherein the second substrate comprises kerf and crack-stop structures disposed around the perimeters of the second chips in the connection zone.

19. The data processing system of claim 18 , wherein the first substrate and the second substrate are substantially the same size and a pitch of the chips on the two substrates are equal.

20. The data processing system of claim 18 , wherein the first substrate further comprises crack-stop structures adjacent to the chip-to-chip interconnects.

Assignees

• IBM

Inventors

• Colgan Evan
• Chainer Timothy J
• Denneau Monty Montague
• Schleupen Kai
• Anzola Diego
• Schultz Mark D
• Berge Layne A

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W46/503

  Located in scribe lines · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10W42/121 Primary

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title