Whole wafer edge seal

Patent metadata

Field	Value
Publication number	US-9589895-B2
Application number	US-201514686904-A
Country	US
Kind code	B2
Filing date	Apr 15, 2015
Priority date	Apr 15, 2015
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

The present invention relates generally to semiconductor devices and more particularly, to a structure and method of creating a non-permeable edge seal around a whole wafer. The edge seal may be located between an inner region of a wafer comprising product chips and an outer edge of the wafer. The edge seal may comprise a fillet region adjacent the inner region, and a dielectric extension adjacent the fillet region. The dielectric extension region may be impermeable to moisture and composed of a dielectric layer on the wafer and a capping layer on the dielectric layer. The fillet region may comprise a lower metal fillet directly on the wafer, a dielectric layer on the lower metal fillet, an upper metal fillet on the dielectric layer, and a capping layer on the upper metal fillet. The fillet region may be adjacent to and in contact with a permeable layer formed on the product region.

First claim

What is claimed is:

1. An edge seal structure encircling a product region and located at a perimeter of a wafer, the edge seal structure comprising:
a permeable layer on a product area of the wafer, wherein an outer edge of the permeable layer is spaced a first distance from an outer edge of the wafer;
a lower metal fillet on the wafer laterally adjacent to an in contact with the permeable layer, wherein an outer edge of the lower metal fillet is spaced a second distance from the outer edge of the wafer, wherein the second distance is smaller than the first distance;
a non-permeable dielectric layer on the permeable layer, on the lower metal fillet, and on an outer region of the wafer adjacent to the lower metal fillet, wherein an outer edge of the dielectric layer is spaced a third distance from the outer edge of the wafer, and wherein the third distance is smaller than the second distance;
an upper metal fillet on the dielectric layer, wherein an outer edge of the upper metal fillet is vertically aligned with an outer edge of the lower metal fillet such that the outer edge the upper metal fillet is the second distance from the outer edge of the wafer; and
a capping layer on the dielectric layer and the upper metal fillet, wherein the capping layer has an outer edge that is vertically aligned with the outer edge of the dielectric layer such that the outer edge of the capping layer is the third distance from the outer edge of the wafer.

2. The structure of claim 1 , wherein the first distance ranges from approximately 1.6 mm to approximately 3 mm.

3. The structure of claim 1 , wherein the second distance ranges from approximately 1.5 mm to approximately 2.5 mm.

4. The structure of claim 1 , wherein the third distance ranges from approximately 0.7 mm to approximately 1.3 mm.

5. The structure of claim 1 , wherein the dielectric layer comprises silicon oxide.

6. The structure of claim 1 , wherein the lower metal fillet and the upper metal fillet comprise copper.

7. The structure of claim 1 , wherein the capping layer comprises silicon oxide.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Bazan Gregory
• Houghton Thomas F

Classifications

• H10P90/128

  by edge treatment, e.g. chamfering · CPC title

• H10W42/00 Primary

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W20/038

  covering conductive structures (H10W20/037 takes precedence) · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title