High memory bandwidth neuromorphic computing system

Patent metadata

Field	Value
Publication number	US-10423877-B2
Application number	US-201615237459-A
Country	US
Kind code	B2
Filing date	Aug 15, 2016
Priority date	Aug 15, 2016
Publication date	Sep 24, 2019
Grant date	Sep 24, 2019

Abstract

Three-dimensional (3D) neuromorphic computing systems are provided. A system includes a logic wafer having a plurality of processors. The system further includes a double-sided interposer bonded to the logic wafer and incorporating a signal port ring for sending and receiving signals. The system also includes a plurality of 3D memory modules bonded to the double-sided interposer. The double-sided interposer is a wafer scale or a panel scale providing communication between the plurality of processors and the plurality of 3D memory modules.

First claim

What is claimed is:

1. A three-dimensional (3D) neuromorphic computing system, comprising:
a logic wafer having a plurality of processors;
a double-sided interposer bonded to the logic wafer, and incorporating a signal port ring for sending and receiving signals; and
a plurality of 3D memory modules bonded to the double-sided interposer,
wherein the double-sided interposer is a wafer scale or a panel scale providing communication between the plurality of processors and the plurality of 3D memory modules.

2. The 3D neuromorphic computing system of claim 1 , wherein the double-sided interposer comprises Si or glass or a flexible material.

3. The 3D neuromorphic computing system of claim 1 , wherein the double-sided interposer is formed into a rectangular shape.

4. The 3D neuromorphic computing system of claim 1 , wherein the double-sided interposer comprises one or more switches for power island control selected from the group consisting of microelectromechanical switches and nanoelectromechanical switches.

5. The 3D neuromorphic computing system of claim 1 , further comprising a plurality of power modules disposed amongst the plurality of 3D memory modules.

6. The 3D neuromorphic computing system of claim 5 , wherein the logic wafer comprises a plurality of fully integrated voltage regulators for connecting to plurality of power modules.

7. The 3D neuromorphic computing system of claim 6 , further comprising a printed circuit board for distributing power to the plurality of power modules.

8. The 3D neuromorphic computing system of claim 1 , wherein the signal port ring comprises active components, the active components comprising optical interconnects.

9. The 3D neuromorphic computing system of claim 1 , further comprising a fluid immersion system.

10. The 3D neuromorphic computing system of claim 1 , wherein the signal port ring is incorporated into the double-sided interposer, adjacent a periphery of the double-sided interposer.

11. The 3D neuromorphic computing system of claim 1 , wherein each of the logic wafer and the double-sided interposer have a substantially circular shape.

12. The 3D neuromorphic computing system of claim 1 , wherein the logic wafer has a substantially circular shape and the double-sided interposer has a substantially rectangular shape with an non-overlapping portion with respect to the logic wafer, the non-overlapping portion comprising peripheral components.

13. The 3D neuromorphic computing system of claim 12 , wherein the peripheral components are selected from the group consisting of power regulators and optical interconnects.

14. The 3D neuromorphic computing system of claim 12 , wherein the double-sided interposer laterally spreads heat generated by the plurality of processors.

15. The 3D neuromorphic computing system of claim 1 , wherein the signals sent and received by the signal port ring include power, data, and control signals.

16. The 3D neuromorphic computing system of claim 1 , further comprising a printed circuit board for providing top-down power distribution to at least the plurality of processors of the logic wafer.

17. A three-dimensional (3D) neuromorphic computing system, comprising:
a logic wafer having a plurality of fully integrated voltage regulators and a plurality of processors;
a double-sided interposer panel bonded to the logic wafer, and incorporating a signal port region for sending and receiving signals;
a plurality of 3D memory modules bonded to the double-sided interposer panel; and
a plurality of power modules disposed amongst the plurality of 3D memory modules, and connected to the plurality of fully integrated voltage regulators,
wherein the double-sided interposer panel provides communication between the plurality of processors and the plurality of 3D memory modules, and
wherein the logic wafer is substantially circular in shape and the double-sided interposer panel is substantially rectangular in shape and has a non-overlapping portion with respect to the logic wafer for incorporating at least a portion of the signal port region.

18. The 3D neuromorphic computing system of claim 17 , wherein the signal power region comprises optical interconnects.

19. The 3D neuromorphic computing system of claim 17 , wherein the double-sided interposer comprises one or more switches for power island control selected from the group consisting of microelectromechanical switches and nanoelectromechanical switches.

20. The 3D neuromorphic computing system of claim 17 , further comprising a printed circuit board for providing top-down power distribution to at least the plurality of processors of the logic wafer.

Assignees

• IBM

Inventors

• Cox Charles E
• Huels Harald
• Kumar Arvind
• Narayanan Pritish
• Ozcan Ahmet S
• Scott J Campbell
• Wilcke Winfried W

Classifications

• H10W70/655

  Fan-out layouts · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title