Methods of making three dimensional NAND devices

Patent metadata

Field	Value
Publication number	US-9305932-B2
Application number	US-201414319283-A
Country	US
Kind code	B2
Filing date	Jun 30, 2014
Priority date	Jun 30, 2014
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A method of making a monolithic three dimensional NAND string includes providing a first stack of alternating first material layers and second material layers over a major surface of a substrate. The first material layers include first silicon oxide layers, the second material layers include second silicon oxide layers, and the first silicon oxide layers have a different etch rate from the second silicon oxide when exposed to the same etching medium. The first stack includes a back side opening, a front side opening, and at least a portion of a floating gate layer, a tunnel dielectric and a semiconductor channel located in the front side opening. The method also includes selectively removing the first material layers through the back side opening to form back side control gate recesses between adjacent second material layers.

First claim

What is claimed is:

1. A method of making a monolithic three dimensional NAND string, comprising:
providing a first stack of alternating first material layers and second material layers over a major surface of a substrate, wherein:
the first material layers comprise first silicon oxide layers, the second material layers comprise second silicon oxide layers, and the first silicon oxide layers have a different etch rate from the second silicon oxide layers when exposed to the same etching medium; and
the first stack comprises a back side opening, a front side opening, and at least a portion of a floating gate layer, a tunnel dielectric and a semiconductor channel located in the front side opening;

selectively removing the first material layers through the back side opening to form back side control gate recesses between adjacent second material layers;
forming a blocking dielectric in the back side control gate recesses through the back side opening; and
forming a plurality of control gate electrodes over the blocking dielectric in the back side control gate recesses through the back side opening.

2. The method of claim 1 , wherein providing the first stack comprises:
providing a second stack of alternating first sacrificial material layers and the first material layers over the major surface of the substrate;
forming the front side opening in the first stack;
forming the floating gate layer, the tunnel dielectric and the semiconductor channel in the front side opening;
forming the back side opening in the second stack;
selectively removing the first sacrificial material layers to form first back side recesses between adjacent first material layers and to expose portions of the floating gate layer in the first back side recesses;
oxidizing or removing the exposed portions of the floating gate layer such that remaining portions of the floating gate layer located adjacent to the first material layers to form discrete floating gate segments; and
filling the first back side recesses through the back side opening with the second material layers to form the first stack.

3. The method of claim 2 , wherein the first sacrificial material layers comprise silicon nitride layers.

4. The method of claim 2 , wherein the floating gate layer comprises a polysilicon floating gate layer, and the step of oxidizing or removing the exposed portions of the floating gate layer comprises oxidizing the exposed portions of the polysilicon floating gate layer to form silicon oxide regions between the discrete floating gate segments.

5. The method of claim 2 , wherein the floating gate layer comprises a polysilicon, metal, metal nitride or metal silicide floating gate layer, and the step of oxidizing or removing the exposed portions of the floating gate layer comprises removing the exposed portions of the floating gate layer to form void regions between the discrete floating gate segments.

6. The method of claim 5 , wherein the step of filling the first back side recesses through the back side opening with the second material layers further fills the respective void regions with the respective second material layers.

7. The method of claim 1 , wherein providing the first stack comprises:
depositing the alternating first material layers and second material layers over the major surface of the substrate;
forming the front side opening in the first stack;
forming the floating gate layer, the tunnel dielectric and the semiconductor channel in the front side opening; and
forming the back side opening in the first stack.

8. The method of claim 7 , further comprising:
selectively removing the second material layers through the back side opening to form second back side recesses between adjacent control gate electrodes and to expose portions of the floating gate layer in the second back side recesses;
oxidizing or removing the exposed portions of the floating gate layer such that remaining portions of the floating gate layer located adjacent to the control gate electrodes to form discrete floating gate segments; and
filling the second back side recesses through the back side opening with insulating material layers.

9. The method of claim 8 , further comprising:
depositing a liner over the blocking dielectric in the back side control gate recesses prior to forming the plurality of control gate electrodes; and
removing the blocking dielectric and the liner from the back side opening thereby exposing a surface of the second material layers in the back side opening.

10. The method of claim 9 , wherein the liner comprises WN or TiN and the control gate electrodes comprise W.

11. The method of claim 8 , wherein the floating gate layer comprises a polysilicon floating gate layer, and the step of oxidizing or removing the exposed portions of the floating gate layer comprises oxidizing the exposed portions of the polysilicon floating gate layer to form silicon oxide regions between the discrete floating gate segments.

12. The method of claim 8 , wherein the floating gate layer comprises a polysilicon, metal, metal nitride or metal silicide floating gate layer, and the step of oxidizing or removing the exposed portions of the floating gate layer comprises removing the exposed portions of the floating gate layer to form void regions between the discrete floating gate segments.

13. The method of claim 12 , wherein the step of filling the second back side recesses through the back side opening with the insulating material layers further fills the respective void regions with the respective insulating material layers.

14. The method of claim 1 , wherein the floating gate layer comprises a polysilicon layer, and further comprising siliciding portions of the polysilicon floating gate layer exposed in the back side control gate recesses prior to forming the blocking dielectric in the back side control gate recesses.

15. The method of claim 1 , wherein the blocking dielectric comprises a plurality of clam shaped regions inside the back side control gate recesses, and the plurality of control gate electrodes are located in the plurality of claim shaped regions in the blocking dielectric.

16. The method of claim 1 , wherein the first silicon oxide layers are deposited by CVD using a dichlorosilane (H 2 SiCl 2 ) source, and the second silicon oxide layers are deposited by CVD using a disilane (Si 2 F 6 ) source.

17. The method of claim 1 , wherein the first silicon oxide layers are deposited by High Aspect Ratio Process (HARP) non-plasma based CVD using TEOS and ozone sources, and the second silicon oxide layers are deposited by high density plasma (HDP) CVD.

18. The method of claim 1 , wherein the first silicon oxide layers comprise borosilicate glass or borophosphosilicate glass layers, and the second silicon oxide layers deposited from a TEOS source.

19. The method of claim 1 , wherein:
the substrate comprises a silicon substrate;
the monolithic three dimensional NAND string is located in an array of monolithic three dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the three dimensional array of NAND strings is located over another memory cell in a second device level of the three dimensional array of NAND strings; and
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon.

20. The method of claim 1 , wherein selectively removing the first material layers comprises selective etching using a HF:H 2 O in a 1:5-15 ratio or a

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Inc

Inventors

• Kanakamedala Senaka Krishna
• Zhang Yanli
• Makala Raghuveer S
• Lee Yao-Sheng
• Alsmeier Johann
• Matamis George

Classifications

• H10P50/283 Primary

  by chemical means · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title