Nitride-based transistors with a protective layer and a low-damage recess

Patent metadata

Field	Value
Publication number	US-11316028-B2
Application number	US-201113022182-A
Country	US
Kind code	B2
Filing date	Feb 7, 2011
Priority date	Jan 16, 2004
Publication date	Apr 26, 2022
Grant date	Apr 26, 2022

Abstract

Transistors are fabricated by forming a nitride-based semiconductor barrier layer on a nitride-based semiconductor channel layer and forming a protective layer on a gate region of the nitride-based semiconductor barrier layer. Patterned ohmic contact metal regions are formed on the barrier layer and annealed to provide first and second ohmic contacts. The annealing is carried out with the protective layer on the gate region. A gate contact is also formed on the gate region of the barrier layer. Transistors having protective layer in the gate region are also provided as are transistors having a barrier layer with a sheet resistance substantially the same as an as-grown sheet resistance of the barrier layer.

First claim

That which is claimed is:

1. A high electron mobility transistor comprising:
a nitride-based channel layer on a top surface of a substrate;
a nitride-based semiconductor barrier layer on a top surface of the nitride-based channel layer,
wherein the barrier layer is either undoped or doped with an n-type dopant;
ohmic contacts directly contacting the barrier layer;
a gate contact having a lowermost portion directly on a top surface of the barrier layer, the gate contact having a T-gate structure, wherein the T-gate structure has first and second opposing sidewalls and first and second wings that extend outwardly from the respective first and second opposing sidewalls;
a patterned protective layer below the first and second wings of the T-gate structure, the patterned protective layer directly on the top surface of the barrier layer, the patterned protective layer spaced apart from the ohmic contacts by gaps,
wherein the patterned protective layer comprises a first portion that is directly under the first wing, a second portion that is directly under the second wing, and a third portion that is not directly under either the first wing or the second wing, wherein the first and second portions comprise a same first material; and
a passivation layer that is on top surfaces of the ohmic contacts and that extends along a side surface of the patterned protective layer within the gaps between the patterned protective layer and the respective ohmic contacts,
wherein the first portion comprises a first layer comprising the first material, the first layer directly contacting the top surface of the barrier layer,
wherein a bottom surface of the first layer that is directly under the first wing and comprising the first material is coplanar with a bottom surface of the lowermost portion of the gate contact,
wherein the first portion further comprises a second layer, the second layer directly contacting the first wing, and
wherein the first material comprises silicon nitride or silicon dioxide.

2. The high electron mobility transistor of claim 1 , wherein the T-gate structure extends through the patterned protective layer and the passivation layer.

3. The high electron mobility transistor of claim 1 :
wherein the nitride-based channel layer comprises a Group III-nitride layer; and
wherein the nitride-based semiconductor barrier layer comprises a Group III-nitride.

4. The high electron mobility transistor of claim 1 , wherein the channel layer has a lower bandgap than the barrier layer, and wherein a contact resistivity of the ohmic contacts is less than about 1 Ω-mm.

5. The high electron mobility transistor of claim 1 :
wherein the channel layer comprises aluminum gallium nitride (AlGaN), gallium nitride (GaN), indium gallium nitride (InGaN), and/or aluminum indium gallium nitride (AlInGaN); and
wherein the barrier layer comprises aluminum nitride (AlN), aluminum indium nitride (AlInN), AlGaN, and/or AlInGaN.

6. The high electron mobility transistor of claim 1 , wherein the barrier layer comprises Al x Ga 1-x N wherein 0<x<1.

7. The high electron mobility transistor of claim 1 , wherein the barrier layer is substantially flat from a first portion of the barrier layer under a first ohmic contact of the ohmic contacts to a second portion of the barrier layer under a second ohmic contact of the ohmic contacts.

8. The high electron mobility transistor of claim 1 , wherein a gate material of the gate contact comprises Ni, Pt, NiSi x , Cu, Pd, Cr, W and/or WSiN, and
wherein a portion of the passivation layer is directly on a top surface of the gate material.

9. The high electron mobility transistor of claim 1 , wherein the passivation layer is directly on a top surface of the third portion of the patterned protective layer.

10. The high electron mobility transistor of claim 1 , wherein the passivation layer comprises a second material that is a different material from the first material.

11. The high electron mobility transistor of claim 1 , wherein the first layer of the first portion of the patterned protective layer has a uniform material composition.

12. The high electron mobility transistor of claim 1 , wherein the second layer comprises a second material that is different from the first material.

13. A high electron mobility transistor comprising:
a nitride-based channel layer on a top surface of a substrate;
a nitride-based semiconductor barrier layer on a top surface of the nitride-based channel layer,
wherein the channel layer and the barrier layer are configured to form a two-dimensional electron gas (2DEG) at a heterojunction between the channel layer and the barrier layer during operation of the high electron mobility transistor;
a first ohmic contact and a second ohmic contact directly contacting the barrier layer;
a patterned protective layer comprising a first material that is separated from the first and second ohmic contacts by respective first and second gaps, the patterned protective layer directly on a top surface of the barrier layer;
a gate contact on the top surface of the barrier layer and extending through the patterned protective layer, the gate contact having first and second opposed sidewalls and first and second wings that extend outwardly from the respective first and second opposed sidewalls,
wherein the first wing of the gate contact is directly on a first portion of the patterned protective layer comprising the first material and the second wing of the gate contact is directly on a second portion of the patterned protective layer comprising the first material; and
a passivation layer that is on top surfaces of the first and second ohmic contacts and that extends along side surfaces of the patterned protective layer within the first and second gaps between the patterned protective layer and the first and second ohmic contacts,
wherein the first and second portions of the patterned protective layer extend beyond sidewalls of the first and second wings of the gate contact in a direction toward respective ones of the first and second ohmic contacts,
wherein a bottom part of the first portion that is closest to the barrier layer comprises the first material, and
wherein the bottom part of the first portion that comprises the first material directly contacts the top surface of the barrier layer and a lowermost portion of the first sidewall of the gate contact, and
wherein the first material comprises silicon nitride and/or silicon dioxide.

14. The high electron mobility transistor of claim 13 , wherein the barrier layer is either undoped or doped with an n-type dopant.

15. The high electron mobility transistor of claim 13 ,
wherein the passivation layer covers the top surfaces of the first and second ohmic contacts.

16. The high electron mobility transistor of claim 13 , wherein a bottom surface of the first portion of the patterned protective layer that is directly under the first wing is coplanar with a bottom surface of the gate contact.

17. The high electron mobility transistor of claim 13 , wherein the first portion further comprises a top part directly contacting the first wing of the gate contact, and
wherein the top part comprises a second material that is different from the first material.

Assignees

• Sheppard Scott T
• Smith Richard Peter
• Ring Zoltan
• Wolfspeed Inc

Inventors

• Sheppard Scott T
• Smith Richard Peter
• Ring Zoltan

Classifications

• H10P10/00

  Bonding of wafers, substrates or parts of devices · CPC title

• H10P95/00 Primary

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D30/4732

  using Group III-V semiconductor material · CPC title

• H10D30/015 Primary

  of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT · CPC title