Reducing read errors by performing mitigation reads to blocks of non-volatile memory

Patent metadata

Field	Value
Publication number	US-2019339902-A1
Application number	US-201815969431-A
Country	US
Kind code	A1
Filing date	May 2, 2018
Priority date	May 2, 2018
Publication date	Nov 7, 2019
Grant date	—

Abstract

A data storage system includes a non-volatile memory array controlled by a controller that records a number of a plurality of like operations targeting a first block among a plurality of blocks in the non-volatile memory array. In response to the number of the plurality of like operations satisfying a threshold, the controller initiates a mitigation read request by recording an identifier of a second block in a high priority request in a mitigation data structure. The controller initiates other mitigation read requests by recording identifiers of other blocks of the non-volatile memory in low priority requests in the mitigation data structure. The controller preferentially services the high priority request from the mitigation data structure over the low priority requests, where servicing the high priority request includes performing a mitigation read to the second block.

First claim

1 . A method in a data storage system including a non-volatile memory array controlled by a controller, the method comprising:
the controller recording a number of a plurality of operations of a same type targeting a first block among a plurality of blocks in the non-volatile memory array; in response to the number of the plurality of operations satisfying a threshold, the controller initiating a mitigation read request by recording an identifier of a different second block in a high priority request in a mitigation data structure; the controller initiating other mitigation read requests by recording identifiers of other blocks of the non-volatile memory array in low priority requests in the mitigation data structure; and the controller preferentially servicing the high priority request from the mitigation data structure over the low priority requests, wherein servicing the high priority request includes performing a mitigation read to the second block.

2 . The method of claim 1 , wherein the plurality of operations comprises a plurality of read operations.

3 . The method of claim 1 , wherein the plurality of operations comprises a plurality of erase operations.

4 . The method of claim 3 , wherein:
the non-volatile memory array includes a plurality of planes; and the first and second blocks are both in a same one of the plurality of planes.

5 . The method of claim 1 , and further comprising:
the controller determining whether or not performing the mitigation read to the second block transitioned the second block from a higher bit error rate state to a lower bit error rate state; and in response to determining that the mitigation read to the second block did not transition the second block from a higher bit error rate state to a lower bit error rate state, the controller calibrating at least one read voltage threshold for the second block.

6 . The method of claim 1 , the controller initiating other mitigation read requests comprises the controller iteratively initiating the other mitigation read requests based on elapsing of a time interval.

7 . A data storage system, comprising:
a controller configured to be coupled to a non-volatile memory array, wherein the controller is configured to perform:
the controller recording a number of a plurality of operations of a same type targeting a first block among a plurality of blocks in the non-volatile memory array;
in response to the number of the plurality of operations satisfying a threshold, the controller initiating a mitigation read request by recording an identifier of a different second block in a high priority request in a mitigation data structure;
the controller initiating other mitigation read requests by recording identifiers of other blocks of the non-volatile memory array in low priority requests in the mitigation data structure; and
the controller preferentially servicing the high priority request from the mitigation data structure over the low priority requests, wherein servicing the high priority request includes performing a mitigation read to the second block.

8 . The data storage system of claim 7 , wherein the plurality of operations comprises a plurality of read operations.

9 . The data storage system of claim 7 , wherein the plurality of operations comprises a plurality of erase operations;

10 . The data storage system of claim 9 , wherein:
the non-volatile memory array includes a plurality of planes; and the first and second blocks are both in a same one of the plurality of planes.

11 . The data storage system of claim 7 , wherein the controller is further configured to perform:
the controller determining whether or not performing the mitigation read to the second block transitioned the second block from a higher bit error rate state to a lower bit error rate state; and in response to determining that the mitigation read to the second block did not transition the second block from a higher bit error rate state to a lower bit error rate state, the controller calibrating at least one read voltage threshold for the second block.

12 . The data storage system of claim 7 , wherein the controller initiating other mitigation read requests comprises the controller iteratively initiating the other mitigation read requests based on elapsing of a time interval.

13 . The data storage system of claim 7 , and further comprising the non-volatile memory array coupled to the controller.

14 . A computer program product, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a controller to cause the controller to perform:
the controller recording a number of a plurality of operations of a same type targeting a first block among a plurality of blocks in the non-volatile memory array; in response to the number of the plurality of operations satisfying a threshold, the controller initiating a mitigation read request by recording an identifier of a different second block in a high priority request in a mitigation data structure; the controller initiating other mitigation read requests by recording identifiers of other blocks of the non-volatile memory array in low priority requests in the mitigation data structure; and the controller preferentially servicing the high priority request from the mitigation data structure over the low priority requests, wherein servicing the high priority request includes performing a mitigation read to the second block.

15 . The program product of claim 14 , wherein the plurality of operations comprises a plurality of read operations.

16 . The program product of claim 14 , wherein the plurality of operations comprises a plurality of erase operations.

17 . The program product of claim 16 , wherein:
the non-volatile memory array includes a plurality of planes; and the first and second blocks are both in a same one of the plurality of planes.

18 . The program product of claim 14 , wherein the program instructions further cause the controller to perform:
the controller determining whether or not performing the mitigation read to the second block transitioned the second block from a higher bit error rate state to a lower bit error rate state; and in response to determining that the mitigation read to the second block did not transition the second block from a higher bit error rate state to a lower bit error rate state, the controller calibrating at least one read voltage threshold for the second block.

19 . The program product of claim 14 , wherein the controller initiating other mitigation read requests comprises the controller iteratively initiating the other mitigation read requests based on elapsing of a time interval.

Assignees

• IBM

Inventors

• Yanes Adalberto G
• Fisher Timothy
• Keller Charles A
• Ma Jason S
• Sallese Kevin E
• Fry Aaron D
• Huynh Van
• Papandreou Nikolaos

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G06F3/0619 Primary

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title