Semiconductor device

Patent metadata

Field	Value
Publication number	US-11302826-B2
Application number	US-202016940682-A
Country	US
Kind code	B2
Filing date	Jul 28, 2020
Priority date	Dec 3, 2015
Publication date	Apr 12, 2022
Grant date	Apr 12, 2022

Abstract

A semiconductor device includes a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor connected to an output node of the first PMOS and NMOS transistors. The first PMOS transistor includes first nanowires, first source and drain regions on opposite sides of each first nanowire, and a first gate completely surrounding each first nanowire. The first NMOS transistor includes second nanowires, second source and drain regions on opposite sides of each second nanowire, and a second gate extending from the first gate and completely surrounding each second nanowire. The second NMOS transistor includes third nanowires, third source and drain regions on opposite sides of each third nanowire, and a third gate, separated from the first and second gates, and completely surrounding each third nanowire. A number of third nanowires is greater than that of first nanowires. The first and second gates share respective first and second nanowires.

First claim

What is claimed is:

1. A semiconductor device, comprising:
first and second multi-bridge channel structures arranged in a second direction and sequentially spaced apart from one another in a first direction that is substantially perpendicular to the second direction;
a first gate structure arranged in the first direction, the first gate structure surrounding the first and second multi-bridge channel structures;
first and second source and drain regions located in the first and second multi-bridge channel structures on respective sides of the first gate structure;
a second gate structure arranged in the first direction and spaced apart from the first gate structure in the second direction, the second gate structure surrounding the first multi-bridge channel structure; and
third source and drain regions located in the first multi-bridge channel structure on respective sides of the second gate structure,
wherein the first and second multi-bridge channel structures are surrounded with the first and second gate structures, respectively, and each of the first and second multi-bridge channel structures comprises a plurality of nano-bridges serving as channels, the plurality of nano-bridges stacked apart from one another in a third direction that is substantially perpendicular to a plane defined by the first direction and the second direction, and
one of the first and second multi-bridge channel structures respectively surrounded by the first and second gate structures comprises a different number of nano-bridges from the other multi-bridge channel structures.

2. The semiconductor device of claim 1 , wherein a number of nano-bridges included in the second multi-bridge channel structure surrounded by the first gate structure is less than a number of nano-bridges included in the first multi-bridge channel structure surrounded by the second gate structure.

3. The semiconductor device of claim 1 , wherein a number of nano-bridges included in the second multi-bridge channel structure surrounded with the first gate structure is less than a number of nano-bridges included in the first multi-bridge channel structure surrounded by the first gate structure.

4. The semiconductor device of claim 1 , a number of nano-bridges included in the first multi-bridge channel structure surrounded by the second gate structure is less than a number of nano-bridges included in the first multi-bridge channel structure surrounded by the first gate structure.

5. The semiconductor device of claim 1 , wherein the first and second multi-bridge channel structures, the first gate structure, and the first and second source and drain regions comprise a first drive transistor and a first load transistor that is electrically connected to the first drive transistor, and the first multi-bridge channel structure, the second gate structure, and the third source and drain regions comprise a first transfer transistor.

6. The semiconductor device of claim 1 , further comprising:
third and fourth multi-bridge channel structures arranged in the second direction and sequentially spaced apart from the second multi-bridge channel structure and from one another in a first direction;
a third gate structure spaced apart from the first gate structure in the second direction and spaced apart from the second gate structure in the first direction, the third gate structure surrounding the third and fourth multi-bridge channel structures;
fifth source and drain regions located in the third and fourth multi-bridge channel structures on respective sides of the third gate structure;
a fourth gate structure spaced apart from the first gate structure in the first direction, the fourth gate structure surrounding the fourth multi-bridge channel structure; and
sixth source and drain regions located in the fourth multi-bridge channel structure on respective sides of the fourth gate structure.

7. The semiconductor device of claim 6 , wherein a number of nano-bridges included in the third multi-bridge channel structure surrounded by the third gate structure is less than a number of nano-bridges included in the fourth multi-bridge channel structure surrounded by the fourth gate structure.

8. The semiconductor device of claim 6 , wherein a number of nano-bridges included in the third multi-bridge channel structure surrounded by the third gate structure is less than a number of nano-bridges included in the fourth multi-bridge channel structure surrounded by the third gate structure.

9. The semiconductor device of claim 6 , a number of nano-bridges included in the fourth multi-bridge channel structure surrounded by the fourth gate structure is less than a number of nano-bridges included in the fourth multi-bridge channel structure surrounded by the third gate structure.

10. The semiconductor device of claim 6 , wherein the third and fourth multi-bridge channel structures, the third gate structure, and the fourth and fifth source and drain regions comprise a second load transistor and a second drive transistor that is electrically connected to the second drive transistor, and the fourth multi-bridge channel structure, the fourth gate structure, and the sixth source and drain regions comprise a second transfer transistor.

11. A semiconductor device, comprising:
first to fourth multi-bridge channel structures arranged in a second direction and sequentially spaced apart from one another in a first direction that is substantially perpendicular to the second direction;
a first gate structure arranged in the first direction, the first gate structure surrounding the first and second multi-bridge channel structures;
first and second source and drain regions located in the first and second multi-bridge channel structures on respective sides of the first gate structure;
a second gate structure arranged in the first direction and spaced apart from the first gate structure in the second direction, the second gate structure surrounding the first multi-bridge channel structure;
third source and drain regions located in the first multi-bridge channel structure on respective sides of the second gate structure;
a third gate structure spaced apart from the first gate structure in the second direction and spaced apart from the second gate structure in the first direction, the third gate structure surrounding the third and fourth multi-bridge channel structures;
fifth source and drain regions located in the third and fourth multi-bridge channel structures on respective sides of the third gate structure;
a fourth gate structure spaced apart from the first gate structure in the first direction, the fourth gate structure surrounding the fourth multi-bridge channel structure; and
sixth source and drain regions located in the fourth multi-bridge channel structure on respective sides of the fourth gate structure,
wherein the first to fourth multi-bridge channel structures are surrounded with the first to fourth gate structures, respectively, and each of the first to fourth multi-bridge channel structures comprises a plurality of nano-bridges serving as channels, the plurality of nano-bridges stacked apart from one another in a third direction that is substantially perpendicular to a plane defined by the first direction and the second direction, and
at least one of the first to fourth multi-bridge channel structures respectively surrounded by the first to fourth gate structures comprises a different number of nano-bridges from the other multi-bridge channel structures.

12. The semiconductor device of claim 11 , wherein a number of nano-bridges included in each of the second and third multi-bridge channel structures surrounded by the first and third gate structures is

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Dong-Hun
• Kim Dong-Won

Classifications

• H10P14/3464

  Nanotubes · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H10D62/292

  Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512) · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title