Static random access memory (SRAM) device for improving electrical characteristics and logic device including the same

Patent metadata

Field	Value
Publication number	US-10374099-B2
Application number	US-201815911148-A
Country	US
Kind code	B2
Filing date	Mar 4, 2018
Priority date	Dec 3, 2015
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

A static random access memory (SRAM) device includes a circuit element that includes a first inverter having a first load transistor and a first drive transistor and a second inverter having a second load transistor and a second drive transistor. Input and output nodes of the first inverter and the second inverter are cross-connected to each other. A first transfer transistor is connected to the output node of the first inverter, and a second transfer transistor is connected to the output nodes of the second inverter. Each of the first and second load transistors, the first and second drive transistors, and the first and second transfer transistors includes a transistor having multi-bridge channels. At least one of the first and second load transistors, the first and second drive transistors, and the first and second transfer transistors includes a transistor having a different number of multi-bridge channels from the other transistors.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first inverter including a first load transistor and a first drive transistor; and
a first transfer transistor connected to an output node of the first inverter,
wherein the first load transistor includes a plurality of first multi-bridge channels, and a first source region and a first drain region on both sides of the first multi-bridge channels,
the first drive transistor includes a plurality of second multi-bridge channels, and a second source region and a second drain region on both sides of the second multi-bridge channels,
the first transfer transistor includes a plurality of third multi-bridge channels, and a third source region and a third drain region on both sides of the third multi-bridge channels,
the number of the plurality of third multi-bridge channels is greater than the number of the plurality of first multi-bridge channels, and
the first, the second and the third source and drain regions have a same height from a substrate.

2. The semiconductor device of claim 1 , wherein the number of the plurality of second multi-bridge channels is greater than the number of the plurality of first multi-bridge channels.

3. The semiconductor device of claim 1 , wherein the number of the plurality of second multi-bridge channels is greater than the number of the plurality of third multi-bridge channels.

4. The semiconductor device of claim 1 , wherein the first load transistor is a p-type metal oxide semiconductor (PMOS) transistor, and
each of the first drive transistor and the first transfer transistor is an n-type metal oxide semiconductor (NMOS) transistor.

5. The semiconductor device of claim 1 , wherein the semiconductor device is a static random access memory (SRAM) device.

6. The semiconductor device of claim 1 , wherein each of the plurality of first, second and third multi-bridge channels includes a plurality of nano-bridges that are stacked on a semiconductor substrate and spaced apart from one another.

7. The semiconductor device of claim 6 , wherein each of the plurality of nano-bridges has a rectangular sectional shape.

8. The semiconductor device of claim 6 , wherein each of the plurality of nano-bridges has a quadrangular sectional shapes.

9. The semiconductor device of claim 1 , further comprising:
a second inverter including a second load transistor and a second drive transistor; and
a second transfer transistor connected to an output node of the second inverter.

10. A semiconductor device, comprising:
a first inverter including a first load transistor and a first drive transistor; and
a first transfer transistor connected to an output node of the first inverter,
wherein the first load transistor includes a plurality of first multi-bridge channels, a first gate, and a first source region and a first drain region on both sides of the first gate and the first multi-bridge channels,
the first drive transistor includes a plurality of second multi-bridge channels, a second gate extended from the first gate, and a second source region and a second drain region on both sides of the second gate and the second multi-bridge channels,
the first transfer transistor includes a plurality of third multi-bridge channels, a third gate separated from the first and the second gates, and a third source region and a third drain region on both sides of the third gate and the third multi-bridge channels,
the number of the plurality of third multi-bridge channels is greater than the number of the plurality of first multi-bridge channels,
the first load transistor is a p-type metal oxide semiconductor (PMOS) transistor,
each of the first drive transistor and the first transfer transistor is an n-type metal oxide semiconductor (NMOS) transistor,
the first gate and the second gate are arranged in a first direction on a substrate, and the first multi-bridge channels are arranged in a second direction that is perpendicular to the first direction and between the first source region and the first drain region on the substrate, and the second multi-bridge channels are arranged in the second direction and between the second source region and the second drain region on the substrate,
the third gate is arranged in the first direction on the substrate, and the third multi-bridge channels are arranged in the second direction and between the third source region and the third drain region on the substrate, and
the first, the second and the third source and drain regions have a same height from the substrate.

11. The semiconductor device of claim 10 , wherein the number of the plurality of second multi-bridge channels is greater than the number of the plurality of first multi-bridge channels.

12. The semiconductor device of claim 10 , wherein the number of the plurality of second multi-bridge channels is greater than the number of the plurality of third multi-bridge channels.

13. The semiconductor device of claim 10 , further comprising:
a second inverter including a second load transistor and a second drive transistor; and
a second transfer transistor connected to an output node of the second inverter.

14. The semiconductor device of claim 13 , wherein the second load transistor includes a plurality of fourth multi-bridge channels,
the second drive transistor includes a plurality of fifth multi-bridge channels,
the second transfer transistor includes a plurality of sixth multi-bridge channels, and
the number of the plurality of sixth multi-bridge channels is greater than the number of the plurality of fourth multi-bridge channels.

15. The semiconductor device of claim 10 , wherein each of the plurality of first, second and third multi-bridge channels includes a plurality of nano-bridges that are stacked on a semiconductor substrate and spaced apart from one another, and
each of the plurality of nano-bridges has a circular sectional shape, an elliptical circular sectional shape or a quadrangular sectional shape.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Dong-Hun
• Kim Dong-Won

Classifications

• H10P14/3464

  Nanotubes · CPC title

• H10P14/3462

  Nanowires · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title

• H01L29/66787

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic