Static random access memory (SRAM) device for improving electrical characteristics and logic device including the same

Patent metadata

Field	Value
Publication number	US-9935204-B2
Application number	US-201615246526-A
Country	US
Kind code	B2
Filing date	Aug 24, 2016
Priority date	Dec 3, 2015
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

A static random access memory (SRAM) device includes a circuit element that includes a first inverter having a first load transistor and a first drive transistor and a second inverter having a second load transistor and a second drive transistor. Input and output nodes of the first inverter and the second inverter are cross-connected to each other. A first transfer transistor is connected to the output node of the first inverter, and a second transfer transistor is connected to the output nodes of the second inverter. Each of the first and second load transistors, the first and second drive transistors, and the first and second transfer transistors includes a transistor having multi-bridge channels. At least one of the first and second load transistors, the first and second drive transistors, and the first and second transfer transistors includes a transistor having a different number of multi-bridge channels from the other transistors.

First claim

What is claimed is:

1. A memory device, comprising:
a circuit element comprising:
a first inverter including a first load transistor, a first output node and a first drive transistor; and

a first transfer transistor connected to the first output node of the first inverter,
wherein the first load transistor, the first drive transistor, and the first transfer transistor each includes a plurality of multi-bridge channels,
wherein at least one of the first load transistor, the first drive transistor, and the first transfer transistor is different from the other transistors of the first inverter in a number of the plurality of multi-bridge channels,
wherein the first load transistor has a first number of the plurality of multi-bridge channels,
wherein the first transfer transistor has a second number of the plurality of multi-bridge channels, and
wherein the second number is greater than the first number.

2. The memory device of claim 1 ,
wherein the circuit element further comprising:
a second inverter including a second load transistor, a second output node and a second drive transistor; and
a second transfer transistor connected to the second output node of the second inverter,

wherein the second load transistor, the second drive transistor, and the second transfer transistor each includes a plurality of multi-bridge channels,
wherein at least one of the second load transistor, the second drive transistor, and the second transfer transistor is different from the other transistors of the second inverter in a number of the plurality of multi-bridge channels,
wherein each of the second load transistor has a third number of the plurality of multi-bridge channels,
wherein each of the second transfer transistor has a fourth number of the plurality of multi-bridge channels, and
wherein the fourth number is greater than the third number.

3. The memory device of claim 2 ,
wherein each of the first drive transistor and the second drive transistor has a fifth number of the plurality of multi-bridge channels, and
wherein the first number is smaller than the fifth number.

4. The memory device of claim 3 ,
wherein the second number is equal to or smaller than the third number.

5. The memory device of claim 2 ,
wherein the plurality of multi-bridge channels is formed of a plurality of nano-bridges stacked on and spaced apart from one another,
wherein the first load transistor, the second load transistor, the first drive transistor, the second drive transistor, the first transfer transistor and the second transfer transistor each further includes a gate structure surrounding each of the plurality of nano-bridges, and
wherein the gate structure includes a gate insulating layer and a gate electrode.

6. The memory device of claim 5 ,
wherein a number of the plurality of nano-bridges included in at least one of the first load transistor, the second load transistor, the first drive transistor, the second drive transistor, the first transfer transistor and the second transfer transistor is different from a number of the plurality of nano-bridges included in the other transistors.

7. The memory device of claim 5 ,
wherein each of the plurality of nano-bridges is formed of a nono-wire or a nano-sheet.

8. The memory device of claim 1 ,
wherein the first load transistor has a first channel width,
wherein the first transfer transistor has a second channel width, and
wherein the second channel width is greater than the first channel width.

9. A static random access memory (SRAM) device, comprising:
a latch circuit comprising a first inverter and a second inverter,
the first inverter comprising a first input node, a first load transistor, a first drive transistor and a first output node,
the second inverter comprising a second input node, a second load transistor, a second drive transistor and a second output node,
the first output node being electrically connected to the second input node and the second output node being electrically connected to the first input node;
a first transfer transistor connected to the first output node; and
a second transfer transistor connected to the second output node,
the first load transistor, the second load transistor, the first drive transistor the second drive transistor, the first transfer transistor and the second transfer transistor each being formed of a multi-bridge channel transistor having a plurality of multi-bridge channels, and
at least one of the first load transistor, the second load transistor, the first drive transistor, the second drive transistor, the first transfer transistor and the second transfer transistor is different from the other transistors in a number of the plurality of multi-bridge channels,
wherein each of the first load transistor and the second load transistor has a first number of the plurality of multi-bridge channels,
wherein each of the first transfer transistor and the second transfer transistor has a second number of the plurality of multi-bridge channels.

10. The SRAM device of claim 9 ,
wherein the first load transistor and the second load transistor each comprises a p-type metal oxide semiconductor (PMOS) transistor, and
wherein the first drive transistor and the second drive transistor each comprises an n-type MOS (NMOS) transistor.

11. The SRAM device of claim 9 ,
wherein the first transfer transistor and the second transfer transistor each comprises an n-type MOS (NMOS) transistor.

12. The SRAM device of claim 9 ,
wherein each of the first drive transistor and the second drive transistor has a third number of the plurality of multi-bridge channels and,
wherein the first number is smaller than the third number.

13. The SRAM device of claim 12 ,
wherein the second number is equal to the third number.

14. The SRAM device of claim 9 ,
wherein the plurality of multi-bridge channels is formed of a plurality of nano-bridges stacked apart from one another,
wherein the first load transistor, the second load transistor, the first drive transistor, the second drive transistor, the first transfer transistor and the second transfer transistor each further includes a gate structure surrounding each of the plurality of nano-bridges,
wherein the gate structure includes a gate insulating layer and a gate electrode.

15. The SRAM device of claim 14 ,
wherein a number of the plurality of nano-bridges included in at least one of the first load transistor, the second load transistor, the first drive transistor, the second drive transistor, the first transfer transistor and the second transfer transistor is different from a number of the plurality of nano-bridges included in each of the other transistors.

16. The SRAM device of claim 9 ,
wherein the second number is greater than the first number.

17. A memory device, comprising:
a plurality of multi-bridge channel structures arranged in a first direction and a second direction that is substantially perpendicular to the first direction, wherein the plurality of multi-bridge channel structures includes a first multi-bridge channel structure, a second multi-bridge channel structure, a third multi-bridge channel structure and a fourth multi-bridge channel structure;
a first gate structure extending in the first direction, the first gate structure surrounding the first multi-bridge channel structure and the second multi-bridge channel structure;
a first source region and a first drain region located in the first multi-bridge channel structure on respective sides of the first gate structure;
a second source region an

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Dong-Hun
• Kim Dong-Won

Classifications

• H10P14/3464

  Nanotubes · CPC title

• H10P14/3462

  Nanowires · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H01L27/1104

  Electricity · mapped topic