Semiconductor device

Patent metadata

Field	Value
Publication number	US-10741676-B2
Application number	US-201916453486-A
Country	US
Kind code	B2
Filing date	Jun 26, 2019
Priority date	Dec 3, 2015
Publication date	Aug 11, 2020
Grant date	Aug 11, 2020

Abstract

A semiconductor device includes a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor connected to an output node of the first PMOS and NMOS transistors. The first PMOS transistor includes first nanowires, first source and drain regions on opposite sides of each first nanowire, and a first gate completely surrounding each first nanowire. The first NMOS transistor includes second nanowires, second source and drain regions on opposite sides of each second nanowire, and a second gate extending from the first gate and completely surrounding each second nanowire. The second NMOS transistor includes third nanowires, third source and drain regions on opposite sides of each third nanowire, and a third gate, separated from the first and second gates, and completely surrounding each third nanowire. A number of third nanowires is greater than that of first nanowires. The first and second gates share respective first and second nanowires.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first p-type metal oxide semiconductor (PMOS) transistor and a first n-type metal oxide semiconductor (NMOS) transistor; and
a second NMOS transistor connected to an output node of the first PMOS transistor and first NMOS transistor,
wherein the first PMOS transistor includes a plurality of first nano-wires, a first source region and a first drain region on both sides of each of the plurality of first nano-wires, and a first gate that completely surrounds each of the plurality of first nano-wires,
the first NMOS transistor includes a plurality of second nano-wires, a second source region and a second drain region on both sides of each of the plurality of second nano-wires, and a second gate extending from the first gate, the second gate completely surrounding each of the plurality of second nano-wires,
the second NMOS transistor includes a plurality of third nano-wires, a third source region and a third drain region on both sides of each of the plurality of third nano-wires, and a third gate separated from the first and the second gates, the third gate completely surrounding each of the plurality of third nano-wires,
a number of the plurality of third nano-wires is greater than a number of the plurality of first nano-wires, and
the first gate and the second gate share respective first nano-wires and second nano-wires.

2. The semiconductor device of claim 1 , wherein:
the first PMOS transistor is a load transistor,
the first NMOS transistor is a drive transistor, and
the second NMOS transistor is a transfer transistor.

3. The semiconductor device of claim 1 , wherein a number of the plurality of second nano-wires is greater than the number of the plurality of first nano-wires.

4. The semiconductor device of claim 1 , wherein a number of the plurality of second nano-wires is greater than the number of the plurality of third nano-wires.

5. The semiconductor device of claim 1 , further comprising:
a second PMOS transistor and a third NMOS transistor; and
a fourth NMOS transistor connected to an output node of the second PMOS transistor and the third NMOS transistor.

6. The semiconductor device of claim 1 , wherein:
the first gate, the second gate and the third gate are arranged in a first direction on a substrate, and
the first nano-wires, the second nano-wires and the third nano-wires are arranged in a second direction that is perpendicular to the first direction on the substrate.

7. A semiconductor device, comprising:
a first p-type metal oxide semiconductor (PMOS) transistor and a first n-type metal oxide semiconductor (NMOS) transistor;
a second NMOS transistor connected to an output node of the first PMOS transistor and first NMOS transistor,
a second PMOS transistor and a third NMOS transistor; and
a fourth NMOS transistor connected to an output node of the second PMOS transistor and the third NMOS transistor,
wherein the first PMOS transistor includes a plurality of first nano-wires, a first source region and a first drain region on both sides of each of the plurality of first nano-wires, and a first gate that completely surrounds each the plurality of first nanowire,
the first NMOS transistor includes a plurality of second nano-wires, a second source region and a second drain region on both sides of the plurality of second nano-wires, and a second gate extended from the first gate, the second gate completely surrounding each of the plurality of second nano-wires,
the second NMOS transistor includes a plurality of third nano-wires, a third source region and a third drain region on both sides of the third nano-wires, and a third gate separated from the first and the second gates, the third gate completely surrounding each of the plurality of third nano-wires,
a number of the plurality of third nano-wires is greater than a number of plurality of first nano-wires, and
the first gate and the second gate share respective first and second nano-wires,
wherein the second PMOS transistor includes a plurality of fourth nano-wires, a fourth source region and a fourth drain region on both sides of each of the plurality of fourth nano-wires, and a fourth gate that completely surrounds each of the plurality of fourth nano-wires,
the third NMOS transistor includes a plurality of fifth nano-wires, a fifth source region and a fifth drain region on both sides of each of the plurality of fifth nano-wires, and a fifth gate extended from the fourth gate, the fifth gate completely surrounding each of the plurality of fifth nano-wires,
the fourth NMOS transistor includes a plurality of sixth nano-wires, a sixth source region and a sixth drain region on both sides of each of the plurality of sixth nano-wires, and a sixth gate separated from the fourth and the fifth gates, the sixth gate completely surrounding each of the plurality of sixth nano-wires,
a number of the plurality of sixth nano-wires is greater than a number of the plurality of fourth nano-wires, and
the fourth gate and the fifth gate share respective fourth and fifth nano-wires.

8. The semiconductor device of claim 7 , wherein:
the first PMOS transistor and the second PMOS transistor are a first load transistor and a second load transistor, respectively,
the first NMOS and the third NMOS transistor are a first drive transistor and a first drive transistor, respectively, and
the second NMOS transistor and the fourth NMOS transistor are a first transfer transistor and a second transfer transistor, respectively.

9. The semiconductor device of claim 7 , wherein a number of the plurality of second nano-wires and a number of the plurality of fifth nano-wires are greater than the number of the plurality of first nano-wires and the number of the plurality of fourth nano-wires, respectively.

10. The semiconductor device of claim 7 , wherein a number of the plurality of second nano-wires and a number of the plurality of fifth nano-wires are greater than the number of the plurality of third nano-wires and the number of the plurality of sixth nano-wires, respectively.

11. The semiconductor device of claim 7 , wherein the first gate, the second gate and the third gate are arranged in a first direction on a substrate, and the first nano-wires, the second nano-wires and the third nano-wires are arranged in a second direction that is perpendicular to the first direction on the substrate.

12. The semiconductor device of claim 7 , wherein the fourth gate, the fifth gate and the sixth gate are arranged in a first direction on a substrate, and the fourth nano-wires, the fifth nano-wires and the sixth nano-wires are arranged in a second direction that is perpendicular to the first direction on the substrate.

13. A semiconductor device, comprising:
a first load transistor and a first drive transistor; and
a first transfer transistor connected to an output node of the first load transistor and the first drive transistor
wherein the first load transistor includes a plurality of first nano-wires, a first gate, and a first source region and a first drain region on both sides of the first gate and the first nano-wires,
the first drive transistor includes a plurality of second nano-wires, a second gate extended from the first gate, and a second source region and a second drain region on both sides of the second gate and the second nano-wires,
the first transfer transistor includes a plurality of third nano-wires, a third gate separated from the first and the second gates, and a third source region and a third drain region on both sides of the third gate and the third nano-wires,
a number of the plurality of third nano-wires is greater a

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Dong-Hun
• Kim Dong-Won

Classifications

• H10P14/3464

  Nanotubes · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H10D62/292

  Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512) · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title