Translation entry invalidation in a multithreaded data processing system

Patent metadata

Field	Value
Publication number	US-9928119-B2
Application number	US-201615082830-A
Country	US
Kind code	B2
Filing date	Mar 28, 2016
Priority date	Dec 22, 2015
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests of a plurality of concurrently executing hardware threads are received in a shared queue. The storage-modifying requests include a translation invalidation request of an initiating hardware thread. The translation invalidation request is removed from the shared queue and buffered in sidecar logic in one of a plurality of sidecars each associated with a respective one of the plurality of hardware threads. While the translation invalidation request is buffered in the sidecar, the sidecar logic broadcasts the translation invalidation request so that it is received and processed by the plurality of processor cores. In response to confirmation of completion of processing of the translation invalidation request by the initiating processor core, the sidecar logic removes the translation invalidation request from the sidecar. Completion of processing of the translation invalidation request at all of the plurality of processor cores is ensured by a broadcast synchronization request.

First claim

What is claimed is:

1. A method of invalidating translation entries without deadlock in a multithreaded data processing system including a plurality of processor cores, the method comprising:
generating, by an initiating thread among a plurality of concurrently executing hardware threads of an initiating processor core among the plurality of processor cores, a translation invalidation request through execution of a corresponding translation invalidation instruction;
pausing dispatch of instructions within the initiating thread that follow the translation invalidation instruction in program order and resuming dispatch of instructions within the initiating thread in response to receipt of an acknowledgment signal confirming completion of processing of the translation invalidation request at the initiating processor core;
receiving, in a shared queue, storage-modifying requests of the plurality of concurrently executing hardware threads of the initiating processor core, wherein the plurality of storage-modifying requests includes a translation invalidation request of an initiating hardware thread among the plurality of hardware threads;
in response to receiving the translation invalidation request in the shared queue, removing the translation invalidation request from the shared queue and buffering the translation invalidation request in sidecar logic;
while the translation invalidation request is buffered in the sidecar logic, the sidecar logic broadcasting the translation invalidation request such that the translation invalidation request is received and processed by the plurality of processor cores;
in response to confirmation of completion of processing of the translation invalidation request by the initiating processor core, the sidecar logic removing the translation invalidation request from the sidecar; and
ensuring completion of processing of the translation invalidation request at all of the plurality of processor cores by a broadcast synchronization request.

2. The method of claim 1 , and further comprising:
in response to snooping broadcast of the translation invalidation request on a system fabric of the data processing system, a translation snoop machine remaining in an active state until a signal confirming completion of processing of the translation invalidation request at a snooping processor core affiliated with the translation snoop machine is received and thereafter returning to an inactive state.

3. The method of claim 1 , wherein ensuring completion includes the sidecar logic broadcasting a translation synchronization request to all of the plurality of processor cores.

4. The method of claim 1 , and further comprising:
the initiating processor core generating the synchronization request by execution of a first synchronization instruction; and
the initiating processor core ordering execution of subsequent memory referent instructions with respect to the first synchronization instruction through execution of a second synchronization instruction.

5. A method of invalidating translation entries without deadlock in a multithreaded data processing system including a plurality of processor cores, the method comprising:
receiving, in a shared queue, storage-modifying requests of a plurality of concurrently executing hardware threads of an initiating processor core, wherein the plurality of storage-modifying requests includes a translation invalidation request of an initiating hardware thread among the plurality of hardware threads, and wherein the translation invalidation request specifies an effective address;
in response to receiving the translation invalidation request in the shared queue, removing the translation invalidation request from the shared queue and buffering the translation invalidation request in sidecar logic;
while the translation invalidation request is buffered in the sidecar logic, the sidecar logic broadcasting the translation invalidation request such that the translation invalidation request is received and processed by the plurality of processor cores;
in response to confirmation of completion of processing of the translation invalidation request by the initiating processor core, the sidecar logic removing the translation invalidation request from the sidecar;
ensuring completion of processing of the translation invalidation request at all of the plurality of processor cores by a broadcast synchronization request;
in response to receiving the translation invalidation request at the initiating processing core:
the initiating processor core invalidating one or more translation entries that translate the effective address;
the initiating processor core waiting for one or more memory referent requests dependent on the one or more translation entries to drain from the initiating processor core; and
thereafter, the initiating processor core transmitting a completion request to the shared queue providing confirmation of completion of processing of the translation invalidation request by the initiating processor core.

6. The method of claim 5 , and further comprising:
in response to the shared queue receiving the completion request, the shared queue ensuring that all older store requests within the shared queue have drained from the shared queue prior to removal of the translation invalidation request from the sidecar.

Assignees

• IBM

Inventors

• Guthrie Guy L
• Shen Hugh
• Williams Derek E

Classifications

• G06F9/3834

  Maintaining memory consistency · CPC title

• G06F2212/683

  Invalidation · CPC title

• G06F9/524 Primary

  Deadlock detection or avoidance · CPC title

• G06F12/1027 Primary

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F9/522

  Barrier synchronisation · CPC title