Deterministic test program generation for evaluating cache coherency
US-2025149103-A1 · May 8, 2025 · US
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Leitner Larry patents
Leitner Larry is listed as an inventor on 9 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Leitner Larry |
| Total patents | 9 |
| First publication | Nov 26, 2020 |
| Latest publication | May 8, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Address translation cache invalidation in a microprocessor
US-11301392-B2 · Apr 12, 2022 · US
Identifying translation errors
US-11243864-B2 · Feb 8, 2022 · US
Software-invisible interrupt for a microprocessor
US-11080122-B2 · Aug 3, 2021 · US
Software-invisible interrupt for a microprocessor
US-2021089382-A1 · Mar 25, 2021 · US
Identifying translation errors
US-2021081296-A1 · Mar 18, 2021 · US
Address translation cache invalidation in a microprocessor
US-10915456-B2 · Feb 9, 2021 · US
Address translation cache invalidation in a microprocessor
US-2021019262-A1 · Jan 21, 2021 · US
Address translation cache invalidation in a microprocessor
US-2020371951-A1 · Nov 26, 2020 · US
Recent patents
Latest publications not already listed above.
No data yet.
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 9 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F12/1036 | 6 |
| G06F12/109 | 6 |
| G06F9/4812 | 4 |
| G06F2212/657 | 4 |
| G06F2212/1024 | 4 |