Transistor having wrap-around source/drain contacts and under-contact spacers

Patent metadata

Field	Value
Publication number	US-11296226-B2
Application number	US-201916654167-A
Country	US
Kind code	B2
Filing date	Oct 16, 2019
Priority date	Oct 16, 2019
Publication date	Apr 5, 2022
Grant date	Apr 5, 2022

Abstract

Embodiments of the invention are directed to a method of forming a semiconductor device. In a non-limiting example, the method includes forming a first channel region over a substrate, forming a second channel region over the first channel region, and forming a merged source or drain (S/D) region over the substrate and adjacent to the first channel region and the second channel region. The merged S/D region is communicatively coupled to the first channel region and the second channel region. A wrap-around S/D contact is formed such that it is on a top surface, sidewalls, and a bottom surface of the merged S/D region.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a first channel region over a substrate;
forming a second channel region over the first channel region;
forming a source or drain (S/D) trench having a S/D trench region and a bottom trench region;
forming a liner within the bottom trench region;
wherein the liner comprises a first liner element on a bottom surface of the bottom trench region;
wherein the liner further comprises a second liner element on sidewalls of the bottom trench region;
forming an under-contact spacer on the first liner element and along first portions of the second liner element such that second portions of the second liner element extend above the under-contact spacer;
forming a merged source or drain (S/D) region within the S/D trench region and adjacent to the first channel region and the second channel region, wherein the merged S/D region comprises a top surface, sidewalls, and a bottom surface;
communicatively coupling the merged S/D region to the first channel region and the second channel region; and
forming a wrap-around S/D contact such that a portion of the wrap-around S/D contact is between the bottom surface of the merged S/D region and a bi-layer bottom spacer comprising the liner and the under-contact spacer.

2. The method of claim 1 , wherein the merged S/D region is configured to extend completely around a circumference of the merged S/D region, wherein the circumference of the merged S/D region comprises the top surface, the sidewalls, and the bottom surface of the merged S/D region.

3. The method of claim 1 , wherein forming the merged S/D region and communicatively coupling the merged S/D region to the first channel region and the second channel region comprise:
epitaxially growing a first S/D region from the first channel region;
epitaxially growing a second S/D region from the second channel region; and
continuing epitaxially growing the first S/D region and the second S/D region until the first S/D region merges with the second S/D region to form the merged S/D region.

4. The method of claim 1 , wherein the bi-layer bottom spacer is positioned between the wrap-around S/D contact and the substrate.

5. The method of claim 1 , wherein the liner comprises a nitride material and the under-contact spacer layer comprises an oxide material.

6. A method of forming a semiconductor device, the method comprising:
forming a channel region over a substrate;
forming a source or drain (S/D) trench over the substrate, wherein the S/D trench comprises a bottom trench region extending below a major surface of the substrate;
forming a liner within the bottom trench region;
wherein the liner comprises a first liner element on a bottom surface of the bottom trench region;
wherein the liner further comprises a second liner element on sidewalls of the bottom trench region;
forming an under-contact spacer on the first liner and along first portions of the second liner element such that second portions of the second liner element extend above the under- contact spacer;
forming a S/D region within the S/D trench and adjacent to the channel region, wherein the S/D region comprises a top surface, sidewalls, and a bottom surface, wherein the S/D region does not extend below the major surface of the substrate and does not extend into the bottom trench region;
communicatively coupling the S/D region to the channel region; and
forming a wrap-around S/D contact such that a portion of the wrap-around S/D contact is beneath the bottom surface of the S/D region.

7. The method of claim 6 , wherein forming the wrap-around contact comprises:
forming a sacrificial wrap-around S/D contact on the top surface, the sidewalls, and the bottom surface of the S/D region;
subsequent to forming the sacrificial S/D wrap-around contact, performing additional fabrication operations; and
subsequent to performing the addition fabrication operations, replacing the sacrificial S/D wrap-around contact with the wrap-around S/D contact.

8. The method of claim 6 , wherein the wrap-around S/D contact is configured to extend completely around a circumference of the S/D region, wherein the circumference of the S/D region comprises the top surface, the sidewalls, and the bottom surface of the S/D region.

9. The method of claim 6 , wherein:
a bi-layer bottom spacer comprises the liner and the under-contact spacer; and
the bit-layer bottom spacer is positioned between the wrap-around S/D contact and the substrate.

10. The method of claim 6 , wherein the liner comprises a nitride material and the under-contact spacer layer comprises an oxide spacer material.

11. The method of claim 6 , wherein:
the channel region comprises a first channel region and a second channel region;
the S/D region comprises a merged S/D region adjacent to the first channel region and the second channel region; and
the merged S/D region is communicatively coupled to the first channel region and the second channel region.

Assignees

• IBM

Inventors

• Song Yi
• Joseph Praveen
• Greene Andrew
• Cheng Kangguo

Classifications

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title